公开(公告)号：US5005068A

公开(公告)日：1991-04-02

申请号：US376953

申请日：1989-07-07

申请人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC分类号： H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

摘要翻译： 一种静态RAM，其具有由构成存储单元的MISFET的扩展栅极电极和由第一字线分开的第二字线构成的第一字线。 RAM具有用于向存储单元提供诸如地电位的固定电位的布线，布线由与用于形成第二字线的层相同的层形成。

公开(公告)号：US5122857A

公开(公告)日：1992-06-16

申请号：US638768

申请日：1991-01-08

申请人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC分类号： H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

公开(公告)号：US5700704A

公开(公告)日：1997-12-23

申请号：US458615

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

摘要翻译： 提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。 特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻 的多晶硅膜。 通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

公开(公告)号：US5652457A

公开(公告)日：1997-07-29

申请号：US351173

申请日：1994-11-30

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5239196A

公开(公告)日：1993-08-24

申请号：US653493

申请日：1991-02-11

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.

摘要翻译： MOSFET静态随机存取存储器（SRAM）单元具有对称结构，具有一对字线。 字线处于第二级多晶硅中，使得它们可能与第一级多晶硅中的驱动晶体管栅极重叠。

公开(公告)号：US5731219A

公开(公告)日：1998-03-24

申请号：US458616

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

摘要翻译： 这里公开了一种半导体集成电路器件，其特征在于包括SRAM，其SRAM具有通过字线和驱动MISFET来控制的转移MISFET构成的存储单元，以及形成该器件的方法。 驱动MISFET的栅电极和存储单元的转移MISFET以及字线分别由不同的导电层形成。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 源极线由与字线的导电层相同的导电层形成。 在驱动MISFET的栅电极上形成抗氧化膜，以减少由这些栅电极的边缘部分的氧化引起的应力，并减少产生的漏电流。 形成在转移MISFET和字线的栅电极上的氧化膜的厚度比形成在驱动MISFET的栅电极上的氧化膜厚，使得数据线焊盘可以形成为与氧化膜和侧面自对准 传输MISFET的栅电极上的壁间隔物。

公开(公告)号：US5656836A

公开(公告)日：1997-08-12

申请号：US460129

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储单元的两个转移MISFET具有彼此间隔开并沿相同方向延伸的两个相应字线连接的各自的栅电极。 由两个字线限定的区域配置有两个驱动MISFET和源极线。

公开(公告)号：US5572480A

公开(公告)日：1996-11-05

申请号：US459961

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  G11C8/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。

公开(公告)号：US5767554A

公开(公告)日：1998-06-16

申请号：US460639

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。