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公开(公告)号：US20120273780A1
公开(公告)日：2012-11-01
申请号：US13547377
申请日：2012-07-12
IPC分类号： H01L29/12
CPC分类号： H01L29/78618 , G02F1/133345 , G02F1/133528 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F1/167 , G02F2201/123 , G09G3/3674 , G09G2310/0286 , H01L27/1225 , H01L27/3262 , H01L29/247 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译： 一个实施例是包括反向交错（底栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。
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公开(公告)号：US20100032665A1
公开(公告)日：2010-02-11
申请号：US12535711
申请日：2009-08-05
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L29/66772 , H01L29/6675 , H01L29/78618 , H01L29/7869
摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译： 一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。
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公开(公告)号：US20100025679A1
公开(公告)日：2010-02-04
申请号：US12511291
申请日：2009-07-29
IPC分类号： H01L33/00
CPC分类号： H01L29/78618 , G02F1/133345 , G02F1/133528 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F1/167 , G02F2201/123 , G09G3/3674 , G09G2310/0286 , H01L27/1225 , H01L27/3262 , H01L29/247 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译： 一个实施例是包括反向交错（底栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。
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公开(公告)号：US20120273779A1
公开(公告)日：2012-11-01
申请号：US13546345
申请日：2012-07-11
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/016 , H01L27/1218 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/15 , H01L27/3225 , H01L27/3241 , H01L27/3248 , H01L27/3258 , H01L29/45 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66742 , H01L29/786 , H01L29/78618
摘要： In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
摘要翻译： 在有源矩阵显示装置中，包括在电路中的薄膜晶体管的电特性是重要的，显示装置的性能取决于电特性。 因此，通过使用包括In，Ga和Zn的氧化物半导体膜用于反向交错薄膜晶体管，可以减小薄膜晶体管的电特性的变化。 通过溅射法连续地形成三层栅极绝缘膜，氧化物半导体层和沟道保护层，而不暴露于空气。 此外，在氧化物半导体层中，与沟道保护膜重叠的区域的厚度大于与导电膜接触的区域的厚度。
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公开(公告)号：US20120108006A1
公开(公告)日：2012-05-03
申请号：US13346118
申请日：2012-01-09
IPC分类号： H01L21/36
CPC分类号： H01L29/66969 , H01L21/46 , H01L27/1225 , H01L29/7869
摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
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公开(公告)号：US20120058599A1
公开(公告)日：2012-03-08
申请号：US13227585
申请日：2011-09-08
CPC分类号： H01L29/7869 , H01L27/1225
摘要： The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity. The semiconductor layer and the source and drain electrode layers are electrically connected to each other through the buffer layer.
摘要翻译： 该半导体器件包括薄膜晶体管，该薄膜晶体管包括栅极电极层，栅极电极层上的栅极绝缘层，栅极绝缘层上的源极电极层和漏极电极层，源电极层上的缓冲层和 漏极电极层和缓冲层上的半导体层。 与栅电极层重叠的半导体层的一部分与栅极绝缘层相接触并且设置在源极电极层和漏极电极层之间。 半导体层是含有铟，镓和锌的氧化物半导体层。 缓冲层含有具有n型导电性的金属氧化物。 半导体层和源极和漏极电极层通过缓冲层彼此电连接。
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公开(公告)号：US20100025677A1
公开(公告)日：2010-02-04
申请号：US12511273
申请日：2009-07-29
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/78606
摘要： To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
摘要翻译： 提供一种包括具有优异的电特性和高可靠性的薄膜晶体管的半导体器件和具有高质量生产率的半导体器件的制造方法。 总而言之，包括使用含有In，Ga和Zn的氧化物半导体膜作为半导体层的反交错（底栅极）薄膜晶体管，沟道保护层设置在与 沟道形成区域，并且在半导体层和源极和漏极之间设置有缓冲层。 通过有意地提供具有比半导体层和源电极和漏电极之间的半导体层更高的载流子浓度的缓冲层来形成欧姆接触。
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公开(公告)号：US20120132910A1
公开(公告)日：2012-05-31
申请号：US13368392
申请日：2012-02-08
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L29/78618
摘要： One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.
摘要翻译： 本发明的目的之一是提供一种使用含有铟（In），镓（Ga）和锌（Zn））的氧化物半导体膜的薄膜晶体管，其中氧化物半导体层和源极之间的接触电阻 并且减少了漏电极，并且提供了制造薄膜晶体管的方法。 通过有意地提供具有比IGZO半导体层和源极和漏极电极层之间的IGZO半导体层更高的载流子浓度的缓冲层来形成欧姆接触。
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公开(公告)号：US20100032668A1
公开(公告)日：2010-02-11
申请号：US12535715
申请日：2009-08-05
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译： 一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 层。 有意地提供具有比半导体层更高的载流子浓度的金属氧化物层作为源极和漏极电极层与半导体层之间的缓冲层，从而形成欧姆接触。
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公开(公告)号：US20100025678A1
公开(公告)日：2010-02-04
申请号：US12511285
申请日：2009-07-29
IPC分类号： H01L29/786 , H01L29/22 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/46 , H01L27/1225 , H01L29/7869
摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
摘要翻译： 本发明的目的是提供一种包括具有良好的电性能和高可靠性的薄膜晶体管的半导体器件，以及一种以高生产率制造半导体器件的方法。 在倒置交错（底栅极）薄膜晶体管中，使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且在半导体层和源之间设置使用金属氧化物层形成的缓冲层， 漏电极层。 有意地提供金属氧化物层作为半导体层与源极和漏极电极层之间的缓冲层，从而获得欧姆接触。
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