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公开(公告)号：US07601572B2
公开(公告)日：2009-10-13
申请号：US11290025
申请日：2005-11-30
CPC分类号： H01L29/78621 , G02F1/13454 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78645 , H01L29/78675 , H01L29/78678 , H01L2924/0002 , H01L2924/00
摘要： In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
摘要翻译： 为了增加开口率，与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，在栅电极和第二布线（154,157）之间设置第一层间绝缘膜（149）和第二层间绝缘膜（150c），以减小寄生电容。
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公开(公告)号：US07294887B2
公开(公告)日：2007-11-13
申请号：US11337514
申请日：2006-01-24
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。
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3.发明授权Method of forming thin film transistors having tapered gate electrode and curved insulating film 失效形成具有锥形栅电极和弯曲绝缘膜的薄膜晶体管的方法公开(公告)号：US07026194B2
公开(公告)日：2006-04-11
申请号：US10317064
申请日：2002-12-12
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。
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公开(公告)号：US20080179674A1
公开(公告)日：2008-07-31
申请号：US11976171
申请日：2007-10-22
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
IPC分类号： H01L27/12
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步骤数量，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。
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公开(公告)号：US20060118874A1
公开(公告)日：2006-06-08
申请号：US11337514
申请日：2006-01-24
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
IPC分类号： H01L27/12
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
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公开(公告)号：US06583471B1
公开(公告)日：2003-06-24
申请号：US09583678
申请日：2000-05-31
IPC分类号： H01L2701
CPC分类号： H01L29/78621 , G02F1/13454 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78645 , H01L29/78675 , H01L29/78678 , H01L2924/0002 , H01L2924/00
摘要： In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
摘要翻译： 为了增加开口率，与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，在栅电极和第二布线（154,157）之间设置第一层间绝缘膜（149）和第二层间绝缘膜（150c），以减小寄生电容。
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7.发明授权Thin film transistors having tapered gate electrode and taped insulating film 有权具有锥形栅电极和带状绝缘膜的薄膜晶体管公开(公告)号：US06515336B1
公开(公告)日：2003-02-04
申请号：US09664359
申请日：2000-09-18
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
IPC分类号： H01L2904
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。
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8.发明授权Method of manufacturing semiconductor device having first and second insulating films 失效制造具有第一和第二绝缘膜的半导体器件的方法公开(公告)号：US07001801B2
公开(公告)日：2006-02-21
申请号：US10413736
申请日：2003-04-15
CPC分类号： H01L29/78621 , G02F1/13454 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78645 , H01L29/78675 , H01L29/78678 , H01L2924/0002 , H01L2924/00
摘要： In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
摘要翻译： 为了增加开口率，与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，第一层间绝缘膜（149）和第二层间绝缘膜（150c）设置在栅电极和第二布线（154,157）之间，以便降低寄生电容。
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公开(公告)号：US07615825B2
公开(公告)日：2009-11-10
申请号：US11976171
申请日：2007-10-22
申请人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
发明人： Hideomi Suzawa , Koji Ono , Hideto Ohnuma , Hirokazu Yamagata , Shunpei Yamazaki
CPC分类号： G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/66757 , H01L29/78621 , H01L29/78633 , H01L29/78645 , H01L2029/7863
摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.
摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。
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公开(公告)号：US20060086982A1
公开(公告)日：2006-04-27
申请号：US11290025
申请日：2005-11-30
IPC分类号： H01L27/12
CPC分类号： H01L29/78621 , G02F1/13454 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78645 , H01L29/78675 , H01L29/78678 , H01L2924/0002 , H01L2924/00
摘要： In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
摘要翻译： 为了增加开口率，与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，第一层间绝缘膜（149）和第二层间绝缘膜（150c）设置在栅电极和第二布线（154,157）之间，以便降低寄生电容。
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