公开(公告)号：US09202929B2

公开(公告)日：2015-12-01

申请号：US12972859

申请日：2010-12-20

申请人： Yasuhiro Jinbo ,  Hideomi Suzawa ,  Hiromichi Godo ,  Shinya Sasagawa

发明人： Yasuhiro Jinbo ,  Hideomi Suzawa ,  Hiromichi Godo ,  Shinya Sasagawa

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L29/66765 ,  H01L29/786 ,  H01L29/78663

摘要： An object is to increase the on-state current of a thin film transistor. A solution is to provide a projection in a back-channel portion of the thin film transistor. The projection is provided so as to be off a tangent in the back-channel portion between a source or a drain and a channel formation region. With the projection, a portion where electric charge is trapped and a path of the on-state current can be apart from each other, so that the on-state current can be increased. The shape of a side surface of the back-channel portion may be curved, or may be represented as straight lines in a cross section. Further, a method for forming such a shape by performing one etching step is provided.

摘要翻译： 目的是增加薄膜晶体管的导通电流。 解决方案是在薄膜晶体管的后通道部分中提供投影。 突起被设置成在源极或漏极之间的后部沟道部分和沟道形成区域之间切断切线。 通过投影，电荷被捕获的部分和导通状态电流的路径可以彼此分开，从而可以增加导通电流。 背沟道部分的侧表面的形状可以是弯曲的，或者可以在横截面中表示为直线。 此外，提供了通过执行一个蚀刻步骤来形成这种形状的方法。

公开(公告)号：US09045831B2

公开(公告)日：2015-06-02

申请号：US12009520

申请日：2008-01-18

申请人： Hideomi Suzawa ,  Koji Ono

发明人： Hideomi Suzawa ,  Koji Ono

IPC分类号： H01L21/302 ,  C23F4/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： C23F4/00 ,  H01L21/28008 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L27/12 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.

公开(公告)号：US08912040B2

公开(公告)日：2014-12-16

申请号：US13012987

申请日：2011-01-25

申请人： Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

发明人： Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

IPC分类号： H01L21/00 ,  H01L21/16 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

摘要翻译： 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US08741702B2

公开(公告)日：2014-06-03

申请号：US12582079

申请日：2009-10-20

申请人： Shunichi Ito ,  Miyuki Hosoba ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

发明人： Shunichi Ito ,  Miyuki Hosoba ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66969 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.

摘要翻译： 目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 在蚀刻步骤中，通过使用蚀刻气体的干蚀刻进行第一蚀刻步骤，并且通过使用蚀刻剂的湿蚀刻进行第二蚀刻步骤。

公开(公告)号：US08735889B2

公开(公告)日：2014-05-27

申请号：US13286280

申请日：2011-11-01

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L29/04

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

摘要翻译： 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US08593603B2

公开(公告)日：2013-11-26

申请号：US11806256

申请日：2007-05-30

申请人： Yuji Egi ,  Takeshi Nishi ,  Kiyofumi Ogino ,  Shinya Sasagawa ,  Motomu Kurata ,  Hideomi Suzawa

发明人： Yuji Egi ,  Takeshi Nishi ,  Kiyofumi Ogino ,  Shinya Sasagawa ,  Motomu Kurata ,  Hideomi Suzawa

IPC分类号： G02F1/1335 ,  G02B27/00

CPC分类号： G02B1/118 ,  C09K11/06 ,  C09K2211/1011 ,  C09K2211/1029 ,  C09K2211/185 ,  G02F1/133502 ,  G02F2201/38 ,  H01L27/3244 ,  H01L51/5281 ,  H05B33/22

摘要： A display device includes an anti-reflection film having a plurality of projections over a display screen surface. An angle made by a base and a slope of each of the plurality of projections is equal to or greater than 84° and less than 90°.

摘要翻译： 显示装置包括在显示屏表面上具有多个突起的防反射膜。 由基座形成的角度和多个突起中的每一个的倾斜度等于或大于84°且小于90°。

公开(公告)号：US08461596B2

公开(公告)日：2013-06-11

申请号：US13288300

申请日：2011-11-03

申请人： Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Shunpei Yamazaki

IPC分类号： H01L27/14 ,  H01L21/00

CPC分类号： H01L29/78621 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/06 ,  H01L29/66765 ,  H01L29/78669

摘要： The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.

摘要翻译： 本发明的目的是提供一种实现生产率和产量提高的有源矩阵液晶显示装置。 在本发明中，使用相同的蚀刻气体选择性地蚀刻包括含有金属材料的导电膜和含有一种导电类型的杂质元素的第二非晶半导体膜和非晶半导体膜的层叠膜，以形成第一 非晶半导体膜1001成锥形。 由此，可以解决像素电极1003的覆盖问题，并且可以用三个光掩模来完成反交错型TFT。

公开(公告)号：US20120326143A1

公开(公告)日：2012-12-27

申请号：US13530392

申请日：2012-06-22

申请人： Takuya Tsurume ,  Hideomi Suzawa ,  Shunpei Yamazaki

发明人： Takuya Tsurume ,  Hideomi Suzawa ,  Shunpei Yamazaki

IPC分类号： H01L33/40 ,  H01L29/12

CPC分类号： H01L27/3246 ,  H01L27/1225 ,  H01L27/3262 ,  H01L51/5237 ,  H01L51/5259

摘要： A light-emitting device in which reduction in performance due to moisture is suppressed is provided. The light-emitting device has a structure in which a partition having a porous structure surrounds each of light-emitting elements. The partition having a porous structure physically adsorbs moisture; therefore, in the light-emitting device, the partition functions as a hygroscopic film at a portion extremely close to the light-emitting element, so that moisture or water vapor remaining in the light-emitting device or entering from the outside can be effectively adsorbed. Thus, reduction in performance of the light-emitting device due to moisture or water vapor can be effectively suppressed.

摘要翻译： 提供抑制湿气性能下降的发光装置。 发光装置具有其中具有多孔结构的分隔件围绕每个发光元件的结构。 具有多孔结构的分隔物物理吸附水分; 因此，在发光装置中，隔板在与发光元件非常接近的部分处起吸湿性的作用，从而能够有效地吸附残留在发光元件中或从外部进入的水分或水蒸汽 。 因此，可以有效地抑制由于水分或水蒸气导致的发光装置的性能的降低。

公开(公告)号：US20120211796A1

公开(公告)日：2012-08-23

申请号：US13465398

申请日：2012-05-07

申请人： Koji Ono ,  Hideomi Suzawa

发明人： Koji Ono ,  Hideomi Suzawa

IPC分类号： H01L33/00 ,  H01L29/78

CPC分类号： H01L27/1214 ,  C23F4/00 ,  H01B1/02 ,  H01B5/14 ,  H01B13/0006 ,  H01B13/0036 ,  H01L21/32136 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/495 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

摘要翻译： 提供适合于大尺寸基板的金属布线。 本发明的特征在于，在绝缘表面上形成至少一层导电膜，在导电膜上形成抗蚀剂图案，并且蚀刻具有抗蚀剂图案的导电膜以形成金属布线，同时控制其锥度 根据偏置功率密度，ICP功率密度，下部电极的温度，压力，蚀刻气体的总流量，或蚀刻气体中的氧气或氯气的比例来确定角度α。 这样形成的金属布线的宽度或长度波动较小，并且可以令人满意地处理基板尺寸的增加。

公开(公告)号：US20120058631A1

公开(公告)日：2012-03-08

申请号：US13295278

申请日：2011-11-14

申请人： Kazuko Ikeda ,  Shinya Sasagawa ,  Hideomi Suzawa ,  Shunpei Yamazaki

发明人： Kazuko Ikeda ,  Shinya Sasagawa ,  Hideomi Suzawa ,  Shunpei Yamazaki

IPC分类号： H01L21/20 ,  H01L21/28

CPC分类号： H01L27/12 ,  H01L29/66757 ,  H01L29/78675 ,  Y10T428/24421

摘要： An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.

摘要翻译： 本发明的目的是提供一种可靠性提高的半导体器件及其制造方法，该半导体器件具有提高的岛状半导体层的端部的缺陷。 一种结构包括设置在基板上的岛状半导体层，设置在岛状半导体层的顶表面和侧表面上的绝缘层以及设置在岛状半导体层上的绝缘层的栅电极 插入其间。 在与岛状半导体层接触的绝缘层中，使与岛状半导体层的侧面接触的区域的介电常数比上述表面的区域低 岛状半导体层。