公开(公告)号：US20050206598A1

公开(公告)日：2005-09-22

申请号：US11115263

申请日：2005-04-27

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3651 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0271 ,  G09G2320/0276 ,  G09G2320/0285

摘要： To provide a display device capable of displaying a good quality image. According to the present invention, there is provided a display device comprising: a display panel composed of a pixel portion in which a plurality of TFTs are arranged in matrix, a source driver, and a gate driver; an image signal processing circuit for processing an image signal input from an external; and a control circuit for controlling the display panel and the image signal processing circuit, characterized in that the image signal processing circuit corrects the image signal on the basis of a correction table and feeds the display panel with the corrected image signal.

公开(公告)号：US09117415B2

公开(公告)日：2015-08-25

申请号：US11115263

申请日：2005-04-27

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3651 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0271 ,  G09G2320/0276 ,  G09G2320/0285

摘要： A display device comprises a display panel composed of a pixel portion in which a plurality of TFTs are arranged in matrix, a source driver, and a gate driver, an image signal processing circuit for processing an image signal input from an external, and a control circuit for controlling the display panel and the image signal processing circuit. The image signal processing circuit corrects the image signal on the basis of a correction table. By feeding the display panel with the corrected image signal, the display device can provide a good quality image.

摘要翻译： 显示装置包括由矩阵状的多个TFT排列的像素部分，源极驱动器和栅极驱动器构成的显示面板，用于处理从外部输入的图像信号的图像信号处理电路，以及控制部 用于控制显示面板和图像信号处理电路的电路。 图像信号处理电路基于校正表来校正图像信号。 通过向显示面板馈送校正后的图像信号，显示装置可以提供高质量的图像。

公开(公告)号：US06909411B1

公开(公告)日：2005-06-21

申请号：US09619478

申请日：2000-07-19

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masaaki Hiroki ,  Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3651 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0271 ,  G09G2320/0276 ,  G09G2320/0285

摘要： To provide a display device capable of displaying a good quality image. According to the present invention, there is provided a display device comprising: a display panel composed of a pixel portion in which a plurality of TFTs are arranged in matrix, a source driver, and a gate driver; an image signal processing circuit for processing an image signal input from an external; and a control circuit for controlling the display panel and the image signal processing circuit, characterized in that the image signal processing circuit corrects the image signal on the basis of a correction table and feeds the display panel with the corrected image signal.

摘要翻译： 提供能够显示优质图像的显示装置。 根据本发明，提供了一种显示装置，包括：由矩阵状排列有多个TFT的像素部，源极驱动器和栅极驱动器构成的显示面板; 用于处理从外部输入的图像信号的图像信号处理电路; 以及用于控制显示面板和图像信号处理电路的控制电路，其特征在于，图像信号处理电路基于校正表校正图像信号，并将校正的图像信号馈送到显示面板。

公开(公告)号：US20060192699A1

公开(公告)日：2006-08-31

申请号：US11368640

申请日：2006-05-12

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M9/00

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03M9/00

摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

公开(公告)号：US06606045B2

公开(公告)日：2003-08-12

申请号：US10043306

申请日：2002-01-14

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M166

CPC分类号： G09G3/3275 ,  G09G3/3233 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/02 ,  H03M1/0607 ,  H03M1/68 ,  H03M1/804

摘要： The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

公开(公告)号：US06420988B1

公开(公告)日：2002-07-16

申请号：US09449535

申请日：1999-11-29

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M166

CPC分类号： G09G3/3275 ,  G09G3/3233 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/02 ,  H03M1/0607 ,  H03M1/68 ,  H03M1/804

摘要： The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

公开(公告)号：US07355534B2

公开(公告)日：2008-04-08

申请号：US11368640

申请日：2006-05-12

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M9/00

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03M9/00

摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

摘要翻译： 在将串行输入的数字数据转换为并行数字数据并输出并行数字数据的数字数据的串行 - 并行转换（SPC）电路中， 采用输入数字数据的最高频率1/2的频率的时钟信号用于操作SPC电路，由此SPC电路的功率消耗，稳定性和可靠性得到改善。

公开(公告)号：US06750792B2

公开(公告)日：2004-06-15

申请号：US10320491

申请日：2002-12-17

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M900

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03M9/00

摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

公开(公告)号：US07049983B2

公开(公告)日：2006-05-23

申请号：US10859984

申请日：2004-06-04

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M9/00

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03M9/00

摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

公开(公告)号：US06512469B1

公开(公告)日：2003-01-28

申请号：US09493682

申请日：2000-01-28

申请人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

发明人： Munehiro Azami ,  Mitsuaki Osame ,  Yutaka Shionoiri ,  Shou Nagao

IPC分类号： H03M900

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03M9/00

摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.