公开(公告)号：US09124834B2

公开(公告)日：2015-09-01

申请号：US13553550

申请日：2012-07-19

申请人： Shunsuke Okura ,  Mitsuo Magane

发明人： Shunsuke Okura ,  Mitsuo Magane

IPC分类号： H04N5/374 ,  H03M1/00 ,  G02F7/00

CPC分类号： H04N5/3742 ,  G02F7/00 ,  H03M1/00 ,  H03M2201/4185 ,  H04N5/359 ,  H04N5/378

摘要： A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

摘要翻译： 根据本发明的固态图像感测装置，其可以减少将图像数字信号从模数转换器传送到寄存器而发生的瞬时电流，以减少噪声潜入模拟数字转换器和像素阵列，包括像素阵列， 垂直扫描电路，多个列ADC，多个寄存器和控制信号生成单元。 控制信号生成单元被提供给各个组，其中列ADC和位于像素阵列一侧的寄存器被分配，并且为包括至少一个组的各个单元生成不同的定时的控制信号 将数字信号从并行运行的列ADC中的寄存器映像。

公开(公告)号：US20130020469A1

公开(公告)日：2013-01-24

申请号：US13553550

申请日：2012-07-19

申请人： Shunsuke Okura ,  Mitsuo Magane

发明人： Shunsuke Okura ,  Mitsuo Magane

IPC分类号： H01L27/146

CPC分类号： H04N5/3742 ,  G02F7/00 ,  H03M1/00 ,  H03M2201/4185 ,  H04N5/359 ,  H04N5/378

摘要： A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

摘要翻译： 根据本发明的固态图像感测装置，其可以减少将图像数字信号从模数转换器传送到寄存器而发生的瞬时电流，以减少噪声潜入模拟数字转换器和像素阵列，包括像素阵列， 垂直扫描电路，多个列ADC，多个寄存器和控制信号生成单元。 控制信号生成单元被提供给各个组，其中列ADC和位于像素阵列一侧的寄存器被分配，并且为包括至少一个组的各个单元生成不同的定时的控制信号 将数字信号从并行运行的列ADC中的寄存器映像。

公开(公告)号：US08665354B2

公开(公告)日：2014-03-04

申请号：US13560811

申请日：2012-07-27

申请人： Shunsuke Okura ,  Mitsuo Magane

发明人： Shunsuke Okura ,  Mitsuo Magane

IPC分类号： H04N3/14

CPC分类号： H04N5/3575 ,  H04N5/3653 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/378

摘要： In a solid-state image pickup device, each pixel at a selected row outputs to a corresponding column signal line a first analog signal in accordance with an amount of electric charges at an electric charge accumulation section in an initial state and a second analog signal in accordance with an amount of photoelectric charges transferred to the electric charge accumulation section. An A/D converter provided at each column performs A/D conversion on the first and second analog signals to output first and second digital signals, respectively. Of first to third latch circuits provided at each column, the first latch circuit takes in and holds the first digital signal outputted from the A/D converter. The second latch circuit takes in and holds the first digital signal held at the first latch circuit. The third latch circuit takes in and holds the second digital signal outputted from the A/D converter.

摘要翻译： 在固态图像拾取装置中，所选行中的每个像素根据初始状态下的电荷积累部分处的电荷量和第一模拟信号中的第二模拟信号将对应的列信号线输出到第一模拟信号 根据转移到电荷累积部分的光电荷的量。 每列提供的A / D转换器对第一和第二模拟信号执行A / D转换，以分别输出第一和第二数字信号。 在每列提供的第一至第三锁存电路中，第一锁存电路接收并保持从A / D转换器输出的第一数字信号。 第二锁存电路接收并保持保持在第一锁存电路的第一数字信号。 第三锁存电路接收并保持从A / D转换器输出的第二数字信号。

公开(公告)号：US20130057737A1

公开(公告)日：2013-03-07

申请号：US13560811

申请日：2012-07-27

申请人： Shunsuke OKURA ,  Mitsuo Magane

发明人： Shunsuke OKURA ,  Mitsuo Magane

IPC分类号： H04N5/335

CPC分类号： H04N5/3575 ,  H04N5/3653 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/378

摘要： In a solid-state image pickup device, each pixel at a selected row outputs to a corresponding column signal line a first analog signal in accordance with an amount of electric charges at an electric charge accumulation section in an initial state and a second analog signal in accordance with an amount of photoelectric charges transferred to the electric charge accumulation section. An A/D converter provided at each column performs A/D conversion on the first and second analog signals to output first and second digital signals, respectively. Of first to third latch circuits provided at each column, the first latch circuit takes in and holds the first digital signal outputted from the A/D converter. The second latch circuit takes in and holds the first digital signal held at the first latch circuit. The third latch circuit takes in and holds the second digital signal outputted from the A/D converter.

摘要翻译： 在固态图像拾取装置中，所选行中的每个像素根据初始状态下的电荷积累部分处的电荷量和第一模拟信号中的第二模拟信号将对应的列信号线输出到第一模拟信号 根据转移到电荷累积部分的光电荷的量。 每列提供的A / D转换器对第一和第二模拟信号执行A / D转换，以分别输出第一和第二数字信号。 在每列提供的第一至第三锁存电路中，第一锁存电路接收并保持从A / D转换器输出的第一数字信号。 第二锁存电路接收并保持保持在第一锁存电路的第一数字信号。 第三锁存电路接收并保持从A / D转换器输出的第二数字信号。

公开(公告)号：US6094069A

公开(公告)日：2000-07-25

申请号：US118839

申请日：1998-07-20

申请人： Mitsuo Magane ,  Masashi Ishii ,  Katsushi Asahina

发明人： Mitsuo Magane ,  Masashi Ishii ,  Katsushi Asahina

IPC分类号： H03K19/0175 ,  H03K19/00

CPC分类号： H03K19/0005

摘要： An object is to provide a semiconductor integrated circuit capable of controlling the output resistance value of an output buffer circuit always at a given value without deteriorating the data transmission quality. D latches (60-63, 65-68) in latch circuit portions (16, 17) in an output resistance control output buffer circuit (2) receive an output resistance control trigger signal (STRB) in common at their respective T inputs. The D latches (60-63) also receive pull-up bit control signals (U0-U3) at their respective D inputs, and the D latches (65-68) also receive pull-down bit control signals (D0-D3) at their respective D inputs. The output resistance value of transistors (QU0-QU3) and transistors (QD0-QD3) is controlled with the data latched in the latch circuit portions (16, 17), respectively. The output resistance control trigger signal (STRB) rises to "H" after a sufficient time has passed after an output resistance control signal determining period in which the pull-down bit control signals (D0-D3) and the pull-up bit control signals (U0-U3) are determined.

摘要翻译： 本发明的目的是提供一种半导体集成电路，其能够将输出缓冲电路的输出电阻值始终控制在给定值，而不会降低数据传输质量。 在输出电阻控制输出缓冲电路（2）中的锁存电路部分（16,17）中的D锁存器（60-63,65-68）在它们各自的T输入处共同接收输出电阻控制触发信号（STRB）。 D锁存器（60-63）还在其各自的D输入端接收上拉位控制信号（U0-U3），D锁存器（65-68）也接收下拉位控制信号（D0-D3） 各自的D输入。 晶体管（QU0-QU3）和晶体管（QD0-QD3）的输出电阻值分别被锁存在锁存电路部分（16,17）中的数据控制。 输出电阻控制触发信号（STRB）在下拉位控制信号（D0-D3）和上拉位控制信号（D0-D3）的输出电阻控制信号确定期间经过足够的时间后上升到“H” （U0-U3）。

公开(公告)号：US20110062985A1

公开(公告)日：2011-03-17

申请号：US12950457

申请日：2010-11-19

申请人： Hiroshi KINOSHITA ,  Mitsuo Magane

发明人： Hiroshi KINOSHITA ,  Mitsuo Magane

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

摘要翻译： 本发明旨在基于外部电阻器的电阻值来调节输出缓冲器的电阻值。 根据外部电阻器和每个电阻调节器之间的电阻比的电位由代码发生器检测。 在代码生成器中，根据检测结果调整用于调整电阻的代码信号。 电阻调节器的电阻值被调整为外部电阻。 此外，通过将每个电阻调节器的电阻值调整为外部电阻器的电阻值的代码信号，调整输出缓冲器的电阻值的电阻。

公开(公告)号：US07863927B2

公开(公告)日：2011-01-04

申请号：US12392517

申请日：2009-02-25

申请人： Hiroshi Kinoshita ,  Mitsuo Magane

发明人： Hiroshi Kinoshita ,  Mitsuo Magane

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

公开(公告)号：US08723998B2

公开(公告)日：2014-05-13

申请号：US13542442

申请日：2012-07-05

申请人： Masanao Maruta ,  Mitsuo Magane

发明人： Masanao Maruta ,  Mitsuo Magane

IPC分类号： H04N5/378

CPC分类号： H04N5/374 ,  H03M1/0624 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

摘要： A solid-state image pickup device includes plural pixels, a voltage generator that generates a reference voltage, plural comparators that are aligned in one direction, and compare respective voltages output from the pixels with the reference voltage, a counter that counts in tandem with a change in the reference voltage generated by the voltage generator, plural buffer circuits that are connected in series with the counter, and each sequentially receives an output of the counter; plural latch circuits that take in a value input to an input terminal thereof according to respective trigger signals output from the comparators, a common signal line that is commonly connected to respective inputs of the latch circuits, and plural signal lines that are connected to respective outputs of the buffer circuits, and allow the output of the counter to propagate therethrough.

摘要翻译： 固体摄像装置包括多个像素，产生参考电压的电压发生器，在一个方向上排列的多个比较器，并将来自像素的各个电压与参考电压进行比较，计数器与 由电压发生器产生的参考电压的变化，与计数器串联连接的多个缓冲电路，并且每个依次接收计数器的输出; 多个锁存电路根据从比较器输出的各自的触发信号，输入到其输入端的值，共同连接到锁存电路的各个输入的公共信号线，以及连接到各个输出的多个信号线 的缓冲电路，并且允许计数器的输出通过其传播。

公开(公告)号：US07969183B2

公开(公告)日：2011-06-28

申请号：US12950457

申请日：2010-11-19

申请人： Hiroshi Kinoshita ,  Mitsuo Magane

发明人： Hiroshi Kinoshita ,  Mitsuo Magane

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

摘要翻译： 本发明旨在基于外部电阻器的电阻值来调节输出缓冲器的电阻值。 根据外部电阻器和每个电阻调节器之间的电阻比的电位由代码发生器检测。 在代码生成器中，根据检测结果调整用于调整电阻的代码信号。 电阻调节器的电阻值被调整为外部电阻。 此外，通过将每个电阻调节器的电阻值调整为外部电阻器的电阻值的代码信号，调整输出缓冲器的电阻值的电阻。

公开(公告)号：US20090243748A1

公开(公告)日：2009-10-01

申请号：US12392517

申请日：2009-02-25

申请人： Hiroshi Kinoshita ,  Mitsuo Magane

发明人： Hiroshi Kinoshita ,  Mitsuo Magane

IPC分类号： H03H7/38

CPC分类号： H03K19/0005

摘要： The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

摘要翻译： 本发明旨在基于外部电阻器的电阻值来调节输出缓冲器的电阻值。 根据外部电阻器和每个电阻调节器之间的电阻比的电位由代码发生器检测。 在代码生成器中，根据检测结果调整用于调整电阻的代码信号。 电阻调节器的电阻值被调整为外部电阻。 此外，通过将每个电阻调节器的电阻值调整为外部电阻器的电阻值的代码信号，调整输出缓冲器的电阻值的电阻。