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公开(公告)号：US6033975A
公开(公告)日：2000-03-07
申请号：US992392
申请日：1997-12-17
IPC分类号： H01L21/265 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/2652 , H01L29/66575
摘要： A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).
摘要翻译： 半导体器件（60）可以包括具有外表面（20）的半导体层（12）。 多个栅极（18）可以设置在半导体层（12）的外表面（20）上方。 隔离罩（30）可以设置在门（18）之上。 植入物筛（40）可以在栅极（18）的隔离盖（30）之间的半导体层（12）的外表面（20）上生长。
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公开(公告)号：US06207500B1
公开(公告)日：2001-03-27
申请号：US09140711
申请日：1998-08-26
申请人： Yin Hu , Dirk Noel Anderson
发明人： Yin Hu , Dirk Noel Anderson
IPC分类号： H01L21336
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/1052
摘要： An improved method for forming a DRAM chip is disclosed. According to this method, a memory cell gate is deposited in a memory cell array area of the DRAM chip. The memory cell gate overlies a first channel area of a substrate. A peripheral gate is deposited in a peripheral area of the DRAM chip. The peripheral gate overlies a second channel area of the substrate. A first dopant is implanted with a first concentration in a first plurality of source and drain regions of the substrate lying predominantly outside the first and second channel areas of the substrate. A sidewall is then formed adjacent to the peripheral gate. Simultaneously, an insulating layer is formed over the memory cell array area of the DRAM chip. A second dopant is implanted with a second concentration in a second plurality of source and drain regions of the substrate within the peripheral area of the DRAM chip. The implant of the second dopant is blocked by the sidewall and the insulating layer. In one embodiment, the first and second dopants are the same, and the dopant concentration in the second plurality of regions is greater than the dopant concentration in the first plurality of regions. This method allows the formation of more heavily doped source and drain regions in the peripheral area of the DRAM chip while keeping the heavily doped regions separated from the channel regions. This reduces diffusion into the channel regions and allows a smaller design rule to be used.
摘要翻译： 公开了一种用于形成DRAM芯片的改进方法。 根据这种方法，存储单元栅极沉积在DRAM芯片的存储单元阵列区域中。 存储单元栅极覆盖衬底的第一沟道区域。 外围栅极沉积在DRAM芯片的外围区域中。 外围栅极覆盖基板的第二通道区域。 在衬底的第一多个源极和漏极区域中以第一浓度注入第一掺杂剂，其主要位于衬底的第一和第二沟道区域的外部。 然后邻近外围栅极形成侧壁。 同时，在DRAM芯片的存储单元阵列区域上形成绝缘层。 第二掺杂剂在DRAM芯片的周边区域内的衬底的第二多个源极和漏极区域中以第二浓度注入。 第二掺杂剂的注入被侧壁和绝缘层阻挡。 在一个实施方案中，第一和第二掺杂剂相同，并且第二多个区域中的掺杂剂浓度大于第一多个区域中的掺杂剂浓度。 该方法允许在DRAM芯片的外围区域中形成更重掺杂的源极和漏极区域，同时保持重掺杂区域与沟道区域分离。 这减少了扩散到通道区域并允许使用较小的设计规则。
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公开(公告)号：US6136700A
公开(公告)日：2000-10-24
申请号：US992268
申请日：1997-12-17
IPC分类号： H01L23/522 , H01L21/306 , H01L21/31 , H01L21/316 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76897 , H01L23/3171 , H01L23/485 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , Y10S257/90
摘要： A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).
摘要翻译： 使用覆盖在基板（12）上的停止层（110），形成与半导体器件（100）的基板（12）的自对准接触（122）。 阻挡层（110）包括选自富硅氮化物，富硅氧化物，富碳氮化物，碳化硅，氮化硼，有机旋涂玻璃，石墨，金刚石，富碳的材料 氧化物，氮化氧化物和有机聚合物。 阻挡层（110）通过有助于相对于用于去除形成在阻挡层（110）上的绝缘层（112）的蚀刻工艺的更大的选择性来促进更好的半导体器件（100）性能。
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