公开(公告)号：US08854548B2

公开(公告)日：2014-10-07

申请号：US14145736

申请日：2013-12-31

Applicant: Silicon Image, Inc.

Inventor： Daekyeung Kim ,  Wooseung Yang ,  Young Il Kim ,  Jeoong Sung Park ,  Hoon Choi

IPC: H04N5/45 ,  H04N21/44 ,  H04N21/4402 ,  G06T1/60 ,  H04N21/2365 ,  H04N21/431 ,  G06T3/40 ,  H04N9/64 ,  H04N21/434

CPC classification number: G06T1/60 ,  G06T3/4084 ,  H04N5/45 ,  H04N9/641 ,  H04N21/2365 ,  H04N21/4316 ,  H04N21/4347 ,  H04N21/44004 ,  H04N21/440263

Abstract: A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video.

Abstract translation: 公开了一种用于画中画视频生成中的存储器减少的机构。 本发明的实施例的方法包括：在发送设备处，在耦合到所述发送设备的接收设备处从所述发送设备接收多个视频流，其中，所述多个视频流中的第一视频流被指定为被显示为主视频 并且指定多个视频流中的一个或多个其它视频流被显示为主视频的一个或多个子视频。 该方法还包括将一个或多个其他视频流变换成一个或多个子视频，将一个或多个子视频暂时保存在压缩帧缓冲器中，并通过像素替换合并主视频和一个或多个子视频 将视频转换为能够使用显示设备在单个屏幕上显示的最终视频图像，其中执行像素替换，使得所述一个或多个子视频占据主视频所占据的屏幕空间像素的一个或多个像素部分。

公开(公告)号：US20140247889A1

公开(公告)日：2014-09-04

申请号：US14273400

申请日：2014-05-08

Applicant: Silicon Image, Inc.

Inventor： Hoon Choi ,  Daekyeung Kim ,  Wooseung Yang ,  Young Il Kim

IPC: H04N19/90 ,  H04N19/46

CPC classification number: H04N21/43635 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/12 ,  H04N5/38 ,  H04N5/4401 ,  H04N19/46 ,  H04N19/90

Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract translation: 本发明的实施例一般涉及以减小的信道格式传输和检测多信道信号。 用于发送数据的方法的实施例包括确定是否要发送第一类型或第二类型的内容数据，其中第一类型的内容数据将以基本频率的第一倍发送，并且第二类型 数据将以基本频率的第二倍发送。 该方法还包括根据内容数据的类型从多个信道中选择一个或多个信道，根据所选择的信道中的内容数据的类型计算基频的第一或第二倍的频率，修改内容 数据以适合于单个输出信道，并且以所选择的基本频率的倍数通过单个输出信道发送修改的数据。

公开(公告)号：US20140241457A1

公开(公告)日：2014-08-28

申请号：US13776577

申请日：2013-02-25

Applicant: Silicon Image, Inc.

Inventor： Daekyeung Kim ,  Daeyun Shim ,  Baegin Sung

IPC: H04L7/00

CPC classification number: G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/0008 ,  H04L25/49

Abstract: Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal.

Abstract translation: 用于交换通信的技术和机制，其各自表示数据和时钟信令的相应组合。 在一个实施例中，编码器逻辑产生第一信号对，包括用差分时钟信号对的第一时钟信号对第一差分数据信号对进行编码。 编码器逻辑还产生第二信号对，包括用相同的差分时钟信号对的第二时钟信号对第二差分数据信号对进行编码。 在另一个实施例中，解码器逻辑接收并解码第一信号对和第二信号对，其中解码产生第一差分数据信号对，第二差分数据信号对和时钟信号。