公开(公告)号：US20220115941A1

公开(公告)日：2022-04-14

申请号：US17066251

申请日：2020-10-08

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Fernando Naim Lavalle Aviles ,  Carlos Jesus Briseno-Vidrios ,  Patrick De Bakker ,  Gabor Marek ,  Charles Guo Lin ,  Peter Onody ,  Tamás Marozsák ,  András V. Horváth

IPC: H02M1/08 ,  H03K17/691 ,  H03K17/18

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

公开(公告)号：US10699995B2

公开(公告)日：2020-06-30

申请号：US15974857

申请日：2018-05-09

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Charles Guo Lin ,  Carlos Briseno-Vidrios

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.