公开(公告)号：US20210159898A1

公开(公告)日：2021-05-27

申请号：US16694100

申请日：2019-11-25

Applicant: Silicon Laboratories Inc.

Inventor： Alan L. Westwick ,  Peter Onody ,  András V. Horváth ,  Tamás Marozsák

IPC: H03K17/16 ,  H03K17/0812 ,  H02P29/024

Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

公开(公告)号：US11057029B2

公开(公告)日：2021-07-06

申请号：US16694100

申请日：2019-11-25

Applicant: Silicon Laboratories Inc.

Inventor： Alan L. Westwick ,  Peter Onody ,  András V. Horváth ,  Tamás Marozsák

IPC: H03K17/16 ,  H03K17/0812 ,  H02P29/024

Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

公开(公告)号：US20220115941A1

公开(公告)日：2022-04-14

申请号：US17066251

申请日：2020-10-08

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Fernando Naim Lavalle Aviles ,  Carlos Jesus Briseno-Vidrios ,  Patrick De Bakker ,  Gabor Marek ,  Charles Guo Lin ,  Peter Onody ,  Tamás Marozsák ,  András V. Horváth

IPC: H02M1/08 ,  H03K17/691 ,  H03K17/18

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

公开(公告)号：US10942217B2

公开(公告)日：2021-03-09

申请号：US16528256

申请日：2019-07-31

Applicant: Silicon Laboratories Inc.

Inventor： Mohammad Al-Shyoukh ,  Peter Onody

IPC: G01R31/02 ,  G01R31/28 ,  H05K1/02 ,  H01R13/6461 ,  G01R31/00 ,  G01R31/50 ,  G01R19/00 ,  G01R31/52 ,  H02M1/00 ,  H02M1/32

Abstract: A method for calibrating an isolator product includes generating a differential pair of signals on a differential pair of nodes at an input of a demodulator circuit of a receiver signal path of a first integrated circuit die of the isolator product based on a received differential pair of signals. The method includes generating a diagnostic output signal having a level corresponding to an average amplitude of the differential pair of signals. The method includes driving the diagnostic output signal to an output terminal of the isolator product. The method may include transmitting a diagnostic signal using a carrier signal having a frequency by a second integrated circuit die via an isolation channel. The method may include, during the transmitting, sweeping the frequency of the carrier signal across a frequency band. The method may include, during the sweeping, capturing the diagnostic output signal via the output terminal.

公开(公告)号：US20210033662A1

公开(公告)日：2021-02-04

申请号：US16528256

申请日：2019-07-31

Applicant: Silicon Laboratories Inc.

Inventor： Mohammad Al-Shyoukh ,  Peter Onody

IPC: G01R31/28 ,  H05K1/02 ,  G01R31/00 ,  H01R13/6461

Abstract: A method for calibrating an isolator product includes generating a differential pair of signals on a differential pair of nodes at an input of a demodulator circuit of a receiver signal path of a first integrated circuit die of the isolator product based on a received differential pair of signals. The method includes generating a diagnostic output signal having a level corresponding to an average amplitude of the differential pair of signals. The method includes driving the diagnostic output signal to an output terminal of the isolator product. The method may include transmitting a diagnostic signal using a carrier signal having a frequency by a second integrated circuit die via an isolation channel. The method may include, during the transmitting, sweeping the frequency of the carrier signal across a frequency band. The method may include, during the sweeping, capturing the diagnostic output signal via the output terminal.

公开(公告)号：US20150042498A1

公开(公告)日：2015-02-12

申请号：US13963788

申请日：2013-08-09

Applicant: Silicon Laboratories Inc.

Inventor： Peter Onody ,  Abdulkerim L. Coban

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/0648 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.

Abstract translation: 通过将连续的电流源对称地围绕阵列的中心来消除第一阶梯度误差，没有电流源分裂。 对应于小输入幅度（中等尺度代码）的连续元件比对应于较大信号幅度的空间跳跃小。 通过将每个当前单元分成两个并将子元素相对于阵列的中心对称放置以解决线性梯度效应，可以减少线性和二阶梯度。 为了解决二阶梯度，当前元素放置遵循模式，使得连续的元素对被选择，其中一对中的一个相对于二阶梯度的零误差轮廓被放置，以便具有正的误差，而第二个 对被放置成具有导致减少的二阶误差累积的负误差。