公开(公告)号：US20220065927A1

公开(公告)日：2022-03-03

申请号：US17009480

申请日：2020-09-01

Applicant: Silicon Laboratories Inc.

Inventor： Daniel de Godoy Peixoto ,  Gregory J. Richmond

IPC: G01R31/317 ,  G01R29/26

Abstract: A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.

公开(公告)号：US10320509B2

公开(公告)日：2019-06-11

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04L7/033 ,  H04J3/14 ,  H04L12/24 ,  H04J3/06

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

公开(公告)号：US20170187481A1

公开(公告)日：2017-06-29

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04J3/14 ,  H04J3/06 ,  H04L7/033 ,  H04L12/24

CPC classification number: H04J3/14 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0331 ,  H04L41/0672

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.