公开(公告)号：US11755096B2

公开(公告)日：2023-09-12

申请号：US17395311

申请日：2021-08-05

申请人： Silicon Laboratories Inc.

发明人： Partha Sarathy Murali ,  Suryanarayana Varma Nallaparaju ,  Kriyangbhai Vinodbhai Shah ,  Venkata Rao Gunturu ,  Subba Reddy Kallam ,  Mani Kumar Kothamasu

IPC分类号： G06F1/32 ,  G06F1/3237 ,  G06F1/3296 ,  H04W52/02 ,  G06F1/3209

CPC分类号： G06F1/3237 ,  G06F1/3209 ,  G06F1/3296 ,  H04W52/0229 ,  H04W52/0235

摘要： A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

公开(公告)号：US11112849B2

公开(公告)日：2021-09-07

申请号：US16599587

申请日：2019-10-11

申请人： Silicon Laboratories Inc.

发明人： Partha Sarathy Murali ,  Suryanarayana Varma Nallaparaju ,  Kriyangbhai Vinodbhai Shah ,  Venkata Rao Gunturu ,  Subba Reddy Kallam ,  Mani Kumar Kothamasu

IPC分类号： G06F1/32 ,  G06F1/3237 ,  G06F1/3296 ,  H04W52/02 ,  G06F1/3209

摘要： A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.