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公开(公告)号：US12045645B2
公开(公告)日：2024-07-23
申请号：US16945871
申请日：2020-08-02
IPC分类号： G06F9/48 , G06F9/30 , G06F9/38 , G06F9/50 , H04L49/90 , H04L65/60 , H04W4/80 , H04W12/06 , H04W80/02 , H04W80/04
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3822 , G06F9/3836 , G06F9/5061 , H04L49/90 , H04L65/60 , H04W4/80 , H04W12/06 , H04W80/02 , H04W80/04
摘要： A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.
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公开(公告)号：US10817200B2
公开(公告)日：2020-10-27
申请号：US15794008
申请日：2017-10-26
发明人： Partha Sarathy Murali , Venkata Siva Prasad Pulagam , Sailaja Dharani Naga Sankabathula , Venkat Rao Gunturu , Subba Reddy Kallam
摘要： A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.
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公开(公告)号：US10757652B2
公开(公告)日：2020-08-25
申请号：US16221325
申请日：2018-12-14
发明人： Sriram Mudulodu , Partha Sarathy Murali , SuryaNarayana Varma Nallaparaju , Logeshwaran Vijayan , Subba Reddy Kallam , Venkat Mattela
摘要： A wireless receiver powers up shortly before the expected arrival of a beacon frame, and upon detection of a beacon frame from an access point the station is associated with and determination of subsequent fields of interest, including at least a TIM field, the receiver powers down. At the previously identified fields of interest, the receiver powers up and uses previously stored values to continue packet demodulation, thereafter examining the TIM field to determine whether the AP has packets to transmit to the station.
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公开(公告)号：US12101658B2
公开(公告)日：2024-09-24
申请号：US16945870
申请日：2020-08-02
CPC分类号： H04W28/0231 , G06F9/30098 , G06F9/3836 , H04W4/80 , H04W16/18 , H04W72/54 , H04W72/563 , H04W84/12
摘要： A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.
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公开(公告)号：US11755096B2
公开(公告)日：2023-09-12
申请号：US17395311
申请日：2021-08-05
发明人： Partha Sarathy Murali , Suryanarayana Varma Nallaparaju , Kriyangbhai Vinodbhai Shah , Venkata Rao Gunturu , Subba Reddy Kallam , Mani Kumar Kothamasu
IPC分类号： G06F1/32 , G06F1/3237 , G06F1/3296 , H04W52/02 , G06F1/3209
CPC分类号： G06F1/3237 , G06F1/3209 , G06F1/3296 , H04W52/0229 , H04W52/0235
摘要： A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
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公开(公告)号：US11112849B2
公开(公告)日：2021-09-07
申请号：US16599587
申请日：2019-10-11
发明人： Partha Sarathy Murali , Suryanarayana Varma Nallaparaju , Kriyangbhai Vinodbhai Shah , Venkata Rao Gunturu , Subba Reddy Kallam , Mani Kumar Kothamasu
IPC分类号： G06F1/32 , G06F1/3237 , G06F1/3296 , H04W52/02 , G06F1/3209
摘要： A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
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公开(公告)号：US11112847B2
公开(公告)日：2021-09-07
申请号：US17006811
申请日：2020-08-29
IPC分类号： G06F1/3228 , G06F1/3234 , G06F9/54 , H04L29/12 , H04W4/12 , H04W4/80 , H04L12/58 , G06F9/445 , H04B1/00 , H04B1/04
摘要： A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.
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公开(公告)号：US12034551B2
公开(公告)日：2024-07-09
申请号：US18195802
申请日：2023-05-10
发明人： Partha Sarathy Murali , Ajay Mantha , Nagaraj Reddy Anakala , Subba Reddy Kallam , Venkat Mattela
摘要： A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
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公开(公告)号：US11665008B2
公开(公告)日：2023-05-30
申请号：US17692027
申请日：2022-03-10
发明人： Partha Sarathy Murali , Ajay Mantha , Nagaraj Reddy Anakala , Subba Reddy Kallam , Venkat Mattela
摘要： A mesh receiver has a wakeup receiver for reception of a wakeup sequence formed by keyed RF or a sequence of wireless packets and gaps, a transmitter forming low speed RF wakeup sequence to other mesh stations, a mesh receiver for reception of high speed WLAN packets, the transmitter sending a wireless ACK packet in response to a wakeup sequence, the mesh receiver thereafter receiving wireless packets from a remote station, the mesh transmitter sending an ACK, the mesh station thereafter identifying a next hop station, and sending a wakeup sequence to that station, after receipt of an ACK, sending the data, the mesh receiver and mesh transmitter thereafter going to sleep.
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公开(公告)号：US11537190B2
公开(公告)日：2022-12-27
申请号：US17006813
申请日：2020-08-29
IPC分类号： G06F1/32 , G06F1/3228 , G06F1/3234 , G06F9/54 , H04W4/12 , H04W4/80 , G06F9/445 , H04B1/00 , H04B1/04 , H04L51/58 , H04L101/622 , G06F1/3203
摘要： A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.
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