METHOD AND APPARATUS FOR PERFORMING ACCESS CONTROL BETWEEN HOST DEVICE AND MEMORY DEVICE

    公开(公告)号:US20200151119A1

    公开(公告)日:2020-05-14

    申请号:US16672509

    申请日:2019-11-03

    Abstract: A method for performing access control between a host device and a memory device, an associated bridge device and a bridge controller thereof are provided, where the method is applicable to the bridge device for coupling the memory device to the host device. The method may include: receiving a first test command; returning failure information; receiving a request command; returning device-related information; receiving a second test command; returning pass information; receiving a capacity-related command; reporting a reported logical address (LA) count of the memory device and a reported sector size of the memory device; and performing bi-directional mapping between a memory device side LA format of a set of LAs at the memory device side corresponding to the memory device and a host device side LA format of a set of LAs at the host device side corresponding to the host device during access operation that the host device performs.

    Computer program product and method and apparatus for controlling access to flash memory card

    公开(公告)号:US11487638B2

    公开(公告)日:2022-11-01

    申请号:US17014169

    申请日:2020-09-08

    Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.

    BRIDGE CONTROL CHIP AND ASSOCIATED SIGNAL PROCESSING METHOD

    公开(公告)号:US20240119017A1

    公开(公告)日:2024-04-11

    申请号:US18109269

    申请日:2023-02-14

    CPC classification number: G06F13/18 G06F13/1621 G06F13/4027

    Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

    Computer program product and method and apparatus for controlling access to flash storage

    公开(公告)号:US11385906B2

    公开(公告)日:2022-07-12

    申请号:US17150244

    申请日:2021-01-15

    Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash storage. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: receiving a host write command from a host side; determining whether the flash storage needs to enter a hibernate state based on at least information regarding a length of data that has been programmed into the flash storage and/or a quantity of host write commands that have been executed after executing the host write command; and instructing the flash storage to enter the hibernate state when the length of data and/or the quantity of host write command meets a triggering condition.

    Bridge control chip and associated signal processing method

    公开(公告)号:US12124388B2

    公开(公告)日:2024-10-22

    申请号:US18109269

    申请日:2023-02-14

    CPC classification number: G06F13/18 G06F13/1621 G06F13/4027

    Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

    Card activation device and methods for authenticating and activating a data storage device by using a card activation device

    公开(公告)号:US11157181B2

    公开(公告)日:2021-10-26

    申请号:US16505159

    申请日:2019-07-08

    Abstract: A card activation device includes a first control unit and a central control unit. In response to a first control command, the central control unit provides first authentication data to the first control unit and the first control unit transmits the first authentication data to the data storage device. After the first authentication data is transmitted to the data storage device, the central control unit provides second authentication data to the first control unit and the first control unit transmits the second authentication data to the data storage device. After the second authentication data is transmitted to the data storage device, the card activation device enters a fully locked state and performs an authentication procedure for authenticating the data storage device. Before the data storage device has passed the authentication procedure, the central control unit is not allowed to transmit any data to the data storage device.

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