公开(公告)号：US12020762B2

公开(公告)日：2024-06-25

申请号：US17576754

申请日：2022-01-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Yuri Tkachev ,  Jinho Kim ,  Cynthia Fung ,  Gilles Festes ,  Bernard Bertello ,  Parviz Ghazavi ,  Bruno Villard ,  Jean Francois Thiery ,  Catherine Decobert ,  Serguei Jourba ,  Fan Luo ,  Latt Tee ,  Nhan Do

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5006

Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

公开(公告)号：US11362218B2

公开(公告)日：2022-06-14

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L27/11517 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11534

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210399127A1

公开(公告)日：2021-12-23

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/11517

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.