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公开(公告)号:US12020762B2
公开(公告)日:2024-06-25
申请号:US17576754
申请日:2022-01-14
Applicant: Silicon Storage Technology, Inc.
Inventor: Yuri Tkachev , Jinho Kim , Cynthia Fung , Gilles Festes , Bernard Bertello , Parviz Ghazavi , Bruno Villard , Jean Francois Thiery , Catherine Decobert , Serguei Jourba , Fan Luo , Latt Tee , Nhan Do
IPC: G11C29/50
CPC classification number: G11C29/50004 , G11C2029/5006
Abstract: A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.
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公开(公告)号:US12243587B2
公开(公告)日:2025-03-04
申请号:US18076129
申请日:2022-12-06
Applicant: Silicon Storage Technology, Inc.
Inventor: Hieu Van Tran , Stephen Trinh , Stanley Hong , Thuan Vu , Anh Ly , Fan Luo
Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
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