公开(公告)号：US12020762B2

公开(公告)日：2024-06-25

申请号：US17576754

申请日：2022-01-14

申请人： Silicon Storage Technology, Inc.

发明人： Yuri Tkachev ,  Jinho Kim ,  Cynthia Fung ,  Gilles Festes ,  Bernard Bertello ,  Parviz Ghazavi ,  Bruno Villard ,  Jean Francois Thiery ,  Catherine Decobert ,  Serguei Jourba ,  Fan Luo ,  Latt Tee ,  Nhan Do

IPC分类号： G11C29/50

CPC分类号： G11C29/50004 ,  G11C2029/5006

摘要： A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

公开(公告)号：US11018147B1

公开(公告)日：2021-05-25

申请号：US16781798

申请日：2020-02-04

申请人： Silicon Storage Technology, Inc.

发明人： Jinho Kim ,  Elizabeth Cuevas ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Catherine Decobert ,  Yuri Tkachev ,  Bruno Villard ,  Nhan Do

IPC分类号： H01L21/00 ,  H01L27/11534 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/788

摘要： A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

公开(公告)号：US11362218B2

公开(公告)日：2022-06-14

申请号：US16910022

申请日：2020-06-23

申请人： Silicon Storage Technology, Inc.

发明人： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC分类号： H01L27/11517 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11534

摘要： A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US20210399127A1

公开(公告)日：2021-12-23

申请号：US16910022

申请日：2020-06-23

申请人： Silicon Storage Technology, Inc.

发明人： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L27/11517

摘要： A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.