-
公开(公告)号：US10797142B2
公开(公告)日：2020-10-06
申请号：US16208288
申请日：2018-12-03
发明人： Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
IPC分类号： H01L29/423 , H01L27/11521 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/788 , H01L21/027 , H01L21/308 , H01L21/3105 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.
-
2.发明授权公开(公告)号：US11968829B2
公开(公告)日：2024-04-23
申请号：US17834746
申请日：2022-06-07
发明人： Zhuoqiang Jia , Leo Xing , Xian Liu , Serguei Jourba , Nhan Do
IPC分类号： H10B41/42 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788
CPC分类号： H10B41/42 , H01L29/40114 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
-
公开(公告)号：US20220231037A1
公开(公告)日：2022-07-21
申请号：US17716950
申请日：2022-04-08
发明人： Serguei Jourba , CATHERINE DECOBERT , FENG ZHOU , JINHO KIM , XIAN LIU , NHAN DO
IPC分类号： H01L27/11517 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788
摘要： A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
-
4.发明申请公开(公告)号：US20200013788A1
公开(公告)日：2020-01-09
申请号：US16422740
申请日：2019-05-24
发明人： Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
IPC分类号： H01L27/11524 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L21/768 , H01L27/088 , H01L21/266 , H01L29/788 , H01L29/78 , H01L29/423
摘要： A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.
-
公开(公告)号：US12020762B2
公开(公告)日：2024-06-25
申请号：US17576754
申请日：2022-01-14
发明人： Yuri Tkachev , Jinho Kim , Cynthia Fung , Gilles Festes , Bernard Bertello , Parviz Ghazavi , Bruno Villard , Jean Francois Thiery , Catherine Decobert , Serguei Jourba , Fan Luo , Latt Tee , Nhan Do
IPC分类号： G11C29/50
CPC分类号： G11C29/50004 , G11C2029/5006
摘要： A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.
-
公开(公告)号：US11594453B2
公开(公告)日：2023-02-28
申请号：US17716950
申请日：2022-04-08
发明人： Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
IPC分类号： H01L21/77 , H01L27/11517 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788
摘要： A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.
-
7.发明申请公开(公告)号：US20200013789A1
公开(公告)日：2020-01-09
申请号：US16578104
申请日：2019-09-20
发明人： Feng Zhou , Jinho Kim , Xian Liu , Serguei Jourba , Catherine Decobert , Nhan Do
IPC分类号： H01L27/11531 , H01L29/423 , H01L29/10 , H01L29/66 , H01L27/11521 , H01L29/78 , H01L29/788
摘要： A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.
-
8.发明申请公开(公告)号：US20190326305A1
公开(公告)日：2019-10-24
申请号：US15957615
申请日：2018-04-19
发明人： FENG ZHOU , Jinho Kim , Xian Liu , Serguei Jourba , Catherine Decobert , Nhan Do
IPC分类号： H01L27/11531 , H01L27/11521 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/66
摘要： A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.
-
9.发明公开公开(公告)号：US20230292504A1
公开(公告)日：2023-09-14
申请号：US17834746
申请日：2022-06-07
发明人： Zhuoqiang Jia , Leo Xing , Xian Liu , Serguei Jourba , Nhan Do
IPC分类号： H01L27/11531 , H01L29/423 , H01L21/28 , H01L29/788 , H01L29/66
CPC分类号： H01L27/11531 , H01L29/42328 , H01L29/40114 , H01L29/7883 , H01L29/66825
摘要： A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
-
10.发明公开公开(公告)号：US20230290864A1
公开(公告)日：2023-09-14
申请号：US17824812
申请日：2022-05-25
发明人： Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/08 , H01L29/788 , H01L29/423 , H01L29/78 , H01L27/11556
CPC分类号： H01L29/66795 , H01L21/823418 , H01L21/823431 , H01L21/823412 , H01L29/0847 , H01L29/66825 , H01L29/788 , H01L29/42328 , H01L29/7851 , H01L27/11556
摘要： A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.015 秒)
