公开(公告)号：US08560899B2

公开(公告)日：2013-10-15

申请号：US12847450

申请日：2010-07-30

申请人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder ,  Glenn Ashley Farrall

发明人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder ,  Glenn Ashley Farrall

IPC分类号： G06F11/00

CPC分类号： G11C29/44 ,  G11C29/024 ,  G11C29/025 ,  G11C2029/0411

摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

摘要翻译： 所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。 在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。 再生地址签名可以与请求的存储器地址位置进行比较。 如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。 因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发， 字线和/或位线是连续的。

公开(公告)号：US20120030531A1

公开(公告)日：2012-02-02

申请号：US12847450

申请日：2010-07-30

申请人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder

发明人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder

IPC分类号： G11C29/04 ,  G06F11/22 ,  G11C8/10

CPC分类号： G11C29/44 ,  G11C29/024 ,  G11C29/025 ,  G11C2029/0411

摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

摘要翻译： 所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。 在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。 再生地址签名可以与请求的存储器地址位置进行比较。 如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。 因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发， 字线和/或位线是连续的。

公开(公告)号：US08880961B2

公开(公告)日：2014-11-04

申请号：US13362433

申请日：2012-01-31

申请人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

发明人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

IPC分类号： G06F11/00

CPC分类号： G06F11/10 ,  G06F11/1645

摘要： A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

摘要翻译： 一种用于处理与具有处理单元的微控制器一起使用的数据的系统和方法，用于向存储器发送输入数据地址作为存储在存储器中的输入数据的读取请求的一部分，从存储器接收输入数据， 多个跟踪信号，基于所述多个跟踪信号产生第一多个签名，从第二微控制器接收第二多个对应签名，将所述第一多个签名的每个签名与所述第二多个对应的每个对应签名进行比较 签名，如果比较产生至少一个失配，则产生第一误差信号，并且利用第一误差信号产生一个或多个禁用信号，以在微控制器的控制下禁止一个或多个设备的操作。

公开(公告)号：US20130198571A1

公开(公告)日：2013-08-01

申请号：US13362433

申请日：2012-01-31

申请人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

发明人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

IPC分类号： G06F11/07 ,  G06F11/34

CPC分类号： G06F11/10 ,  G06F11/1645

摘要： A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

摘要翻译： 一种用于处理与具有处理单元的微控制器一起使用的数据的系统和方法，用于向存储器发送输入数据地址作为存储在存储器中的输入数据的读取请求的一部分，从存储器接收输入数据， 多个跟踪信号，基于所述多个跟踪信号产生第一多个签名，从第二微控制器接收第二多个对应签名，将所述第一多个签名的每个签名与所述第二多个对应的每个对应签名进行比较 签名，如果比较产生至少一个失配，则产生第一误差信号，并且利用第一误差信号产生一个或多个禁用信号，以在微控制器的控制下禁止一个或多个设备的操作。

公开(公告)号：US08954794B2

公开(公告)日：2015-02-10

申请号：US13488571

申请日：2012-06-05

申请人： Neil Hastie ,  Simon Brewerton

发明人： Neil Hastie ,  Simon Brewerton

IPC分类号： G06F11/00

CPC分类号： G06F11/1641 ,  G06F11/1679

摘要： Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

摘要翻译： 实施例涉及用于检测在相同输入数据中操作的CPU内的寄存器损坏的系统和方法，其使得能够对不同CPU的至少一组相应寄存器中的至少一组的内容进行非侵入式读访问和比较，从而以相应的形式检测损坏的寄存器 注册内容不一致。

公开(公告)号：US20120023389A1

公开(公告)日：2012-01-26

申请号：US12839503

申请日：2010-07-20

申请人： Simon Brewerton ,  Neil Hastie

发明人： Simon Brewerton ,  Neil Hastie

IPC分类号： G06F7/02

CPC分类号： G06F11/1641 ,  G06F11/1679 ,  G06F17/505 ,  G06F2217/14

摘要： Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

摘要翻译： 公开了处理器，微处理器和逻辑块系统和方法，错误检测系统和方法以及集成电路。 在一个实施例中，基于逻辑的计算系统包括第一处理核心; 从所述第一处理核心产生并包括所述第一处理核心的反相逻辑等效物的第二处理核心，使得所述第二处理核心的输出是所述第一处理核心的输出的补码; 以及比较器逻辑，被耦合以接收第一和第二处理核的输出作为输入，并且如果第二处理核的输出不是第一处理核的输出的补码，则提供错误输出。

公开(公告)号：US20130326289A1

公开(公告)日：2013-12-05

申请号：US13488571

申请日：2012-06-05

申请人： Neil Hastie ,  Simon Brewerton

发明人： Neil Hastie ,  Simon Brewerton

IPC分类号： G06F11/07

CPC分类号： G06F11/1641 ,  G06F11/1679

摘要： Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

摘要翻译： 实施例涉及用于检测在相同输入数据中操作的CPU内的寄存器损坏的系统和方法，其使得能够对不同CPU的至少一组相应寄存器中的至少一组的内容进行非侵入式读访问和比较，从而以相应的形式检测损坏的寄存器 注册内容不一致。

公开(公告)号：US20110208948A1

公开(公告)日：2011-08-25

申请号：US12710616

申请日：2010-02-23

申请人： Richard Knight ,  Neil Hastie ,  Simon Brewerton ,  Glenn Farrall

发明人： Richard Knight ,  Neil Hastie ,  Simon Brewerton ,  Glenn Farrall

IPC分类号： G06F9/30 ,  G06F3/00 ,  G06F15/76 ,  G06F9/312

CPC分类号： G06F11/1497 ,  G06F11/1695 ,  G06F2201/83

摘要： Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others.

摘要翻译： 实施例涉及在利用时间上分离的冗余执行的鲁棒计算期间从接口外围设备或其他共享资源读取和写入系统和方法。 实施例可用于与汽车，银行和金融，航空航天，国防，互联网支付等有关的安全相关应用。

公开(公告)号：US08516356B2

公开(公告)日：2013-08-20

申请号：US12839503

申请日：2010-07-20

申请人： Simon Brewerton ,  Neil Hastie

发明人： Simon Brewerton ,  Neil Hastie

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F9/455 ,  G06F17/50

CPC分类号： G06F11/1641 ,  G06F11/1679 ,  G06F17/505 ,  G06F2217/14

摘要： Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

摘要翻译： 公开了处理器，微处理器和逻辑块系统和方法，错误检测系统和方法以及集成电路。 在一个实施例中，基于逻辑的计算系统包括第一处理核心; 从所述第一处理核心产生并包括所述第一处理核心的反相逻辑等效物的第二处理核心，使得所述第二处理核心的输出是所述第一处理核心的输出的补码; 以及比较器逻辑，被耦合以接收第一和第二处理核的输出作为输入，并且如果第二处理核的输出不是第一处理核的输出的补码，则提供错误输出。

公开(公告)号：US20050149699A1

公开(公告)日：2005-07-07

申请号：US11053096

申请日：2005-02-07

申请人： Erik Norden ,  Roger Arnold ,  Robert Ober ,  Neil Hastie

发明人： Erik Norden ,  Roger Arnold ,  Robert Ober ,  Neil Hastie

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/3867

摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

摘要翻译： 可变长度指令流水线包括可以包括在可变长度指令流水线中以避免流水线停顿的可选扩展阶段。 当不需要缩短管道长度时，从可变长度指令流水线中移除扩展级，这减少了与长流水线相关联的延迟和其他问题。 例如，在本发明的一个实施例中，可变长度指令流水线包括第一流水线阶段，第一扩展阶段和第二流水线阶段。 第二流水线级被配置为如果第一扩展级保持指令，则选择性地接收来自第一流水线级或第一扩展级的指令。