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    System and method of computation by signature analysis
    1.
    发明授权
    System and method of computation by signature analysis 有权
    系统和计算方法通过签名分析

    公开(公告)号：US08880961B2

    公开(公告)日：2014-11-04

    申请号：US13362433

    申请日：2012-01-31

    申请人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

    发明人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10 ,  G06F11/1645

    摘要： A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

    摘要翻译： 一种用于处理与具有处理单元的微控制器一起使用的数据的系统和方法，用于向存储器发送输入数据地址作为存储在存储器中的输入数据的读取请求的一部分，从存储器接收输入数据， 多个跟踪信号，基于所述多个跟踪信号产生第一多个签名，从第二微控制器接收第二多个对应签名，将所述第一多个签名的每个签名与所述第二多个对应的每个对应签名进行比较 签名，如果比较产生至少一个失配，则产生第一误差信号，并且利用第一误差信号产生一个或多个禁用信号，以在微控制器的控制下禁止一个或多个设备的操作。

    System and Method of Computation by Signature Analysis
    2.
    发明申请
    System and Method of Computation by Signature Analysis 有权
    通过签名分析计算的系统和方法

    公开(公告)号：US20130198571A1

    公开(公告)日：2013-08-01

    申请号：US13362433

    申请日：2012-01-31

    申请人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

    发明人： Simon Brewerton ,  Neil Hastie ,  Glenn Farrall ,  Boyko Traykov ,  Antonio Vilela

    IPC分类号： G06F11/07 ,  G06F11/34

    CPC分类号： G06F11/10 ,  G06F11/1645

    摘要： A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

    摘要翻译： 一种用于处理与具有处理单元的微控制器一起使用的数据的系统和方法，用于向存储器发送输入数据地址作为存储在存储器中的输入数据的读取请求的一部分，从存储器接收输入数据， 多个跟踪信号，基于所述多个跟踪信号产生第一多个签名，从第二微控制器接收第二多个对应签名，将所述第一多个签名的每个签名与所述第二多个对应的每个对应签名进行比较 签名，如果比较产生至少一个失配，则产生第一误差信号，并且利用第一误差信号产生一个或多个禁用信号，以在微控制器的控制下禁止一个或多个设备的操作。

    Safe memory storage by internal operation verification
    5.
    发明授权
    Safe memory storage by internal operation verification 有权
    通过内部操作验证安全内存存储

    公开(公告)号：US08560899B2

    公开(公告)日：2013-10-15

    申请号：US12847450

    申请日：2010-07-30

    申请人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder ,  Glenn Ashley Farrall

    发明人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder ,  Glenn Ashley Farrall

    IPC分类号： G06F11/00

    CPC分类号： G11C29/44 ,  G11C29/024 ,  G11C29/025 ,  G11C2029/0411

    摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

    摘要翻译： 所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。 在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。 再生地址签名可以与请求的存储器地址位置进行比较。 如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。 因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发， 字线和/或位线是连续的。

    Safe Memory Storage By Internal Operation Verification
    6.
    发明申请
    Safe Memory Storage By Internal Operation Verification 有权
    通过内部操作验证安全内存存储

    公开(公告)号：US20120030531A1

    公开(公告)日：2012-02-02

    申请号：US12847450

    申请日：2010-07-30

    申请人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder

    发明人： Simon Brewerton ,  Neil Hastie ,  Paul Hubbert ,  Klaus Oberlaender ,  Robert Wiesner ,  Antonio Vilela ,  Alfred Eder

    IPC分类号： G11C29/04 ,  G06F11/22 ,  G11C8/10

    CPC分类号： G11C29/44 ,  G11C29/024 ,  G11C29/025 ,  G11C2029/0411

    摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

    摘要翻译： 所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。 在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。 再生地址签名可以与请求的存储器地址位置进行比较。 如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。 因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发， 字线和/或位线是连续的。

    Methods and Systems for Measuring I/O Signals
    7.
    发明申请
    Methods and Systems for Measuring I/O Signals 有权
    测量I / O信号的方法和系统

    公开(公告)号：US20120110374A1

    公开(公告)日：2012-05-03

    申请号：US12915396

    申请日：2010-10-29

    申请人： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

    发明人： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

    IPC分类号： G06F11/34

    CPC分类号： G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

    摘要： Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

    摘要翻译： 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

    Methods and systems for measuring I/O signals
    8.
    发明授权
    Methods and systems for measuring I/O signals 有权
    用于测量I / O信号的方法和系统

    公开(公告)号：US08539278B2

    公开(公告)日：2013-09-17

    申请号：US12915396

    申请日：2010-10-29

    申请人： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

    发明人： Simon Brewerton ,  Patrick Leteinturier ,  Oreste Bernardi ,  Antonio Vilela ,  Klaus Scheibert ,  Jens Barrenscheen

    IPC分类号： G06F11/00

    CPC分类号： G06F11/263 ,  G06F11/0739 ,  G06F11/0754 ,  G06F11/3013 ,  G06F11/3068

    摘要： Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

    摘要翻译： 本发明的一些实施例涉及一种嵌入式处理系统。 该系统包括用于存储多个操作指令的存储器单元和耦合到存储器单元的处理单元。 处理单元可以执行与各个操作指令相对应的逻辑操作。 输入/输出（I / O）接口接收第一时变波形并提供基于第一时变波形的I / O信号。 比较单元，耦合到所述处理单元，并且适于基于所述I / O信号是否与参考信号具有预定关系来选择性地确定错误信号，其中所述预定关系在正常操作期间成立，但是当意外 事件发生并导致至少一个I / O信号和参考信号的意外变化。

    Enhanced scalable CPU for coded execution of SW in high-dependable safety relevant applications
    9.
    发明授权
    Enhanced scalable CPU for coded execution of SW in high-dependable safety relevant applications 有权
    增强的可扩展CPU，用于在高可靠性安全相关应用程序中对SW进行编码执行

    公开(公告)号：US08621273B2

    公开(公告)日：2013-12-31

    申请号：US12954977

    申请日：2010-11-29

    申请人： Rafael Zalman ,  Antonio Vilela ,  Alexander Griessing ,  Wilhard Wendorff

    发明人： Rafael Zalman ,  Antonio Vilela ,  Alexander Griessing ,  Wilhard Wendorff

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10 ,  G06F11/2236 ,  G06F11/25

    摘要： Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications.

    摘要翻译： 本发明的一些实施例涉及被配置为包括可配置硬件扩展的单个处理器，其被布置在数据路径中，该数据路径被配置为选择性地提供编码数据或原始数据，其允许两种操作模式。 在高性能模式下，通过使用用于处理扩展数据的硬件扩展（即附加的原始数据），硬件扩展允许增加的处理带宽。 在安全完整性模式下，硬件扩展允许通过处理自检程序和自检数据，与处理器执行SBST并发处理编码数据。 因此，单通道处理器提供单核系统，其可以选择性地实现用于安全相关应用的高安全完整性级别（例如，SIL3）或者用于非安全相关应用的高性能。

    Error signal handling unit, device and method for outputting an error condition signal
    10.
    发明授权
    Error signal handling unit, device and method for outputting an error condition signal 有权
    误差信号处理单元，用于输出错误状态信号的装置和方法

    公开(公告)号：US08786424B2

    公开(公告)日：2014-07-22

    申请号：US13397035

    申请日：2012-02-15

    申请人： Antonio Vilela ,  Andre Roger

    发明人： Antonio Vilela ,  Andre Roger

    IPC分类号： G08B23/00

    CPC分类号： B60W50/0225 ,  B60W50/0205 ,  B60W2050/0006

    摘要： An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

    摘要翻译： 错误信号处理包括被配置为从外部设备接收指示外部设备中的错误状况的错误信号的电路。 电路还被配置为接收指示在外部设备中减轻错误状况的恢复信号，或指示可以减轻外部设备中的错误状况。 此外，电路还被配置为响应于误差信号的接收而输出基于误差信号的误差条件信号，如果在从接收到误差信号的给定延迟时间内，电路没有接收到恢复信号， 否则省略输出错误状态信号。