公开(公告)号：US5295257A

公开(公告)日：1994-03-15

申请号：US705460

申请日：1991-05-24

申请人： Simon Y. Berkovich ,  Steven A. Haaser ,  Henry C. Yee ,  Chris J. Walter

发明人： Simon Y. Berkovich ,  Steven A. Haaser ,  Henry C. Yee ,  Chris J. Walter

IPC分类号： G06F1/12 ,  G06F1/14

CPC分类号： G06F1/14 ,  G06F1/12

摘要： A method for synchronizing a distributed multiple clock system in which the first clock to reach a first predetermined number of counts generates a polling request signal. The remaining clocks compare the content of their counters to determine if they are in synchronization with the clock that generated the polling request signal. Each clock will place itself inactive if it determines it is out of synchronization with the active clocks. The first active clock to reach a second predetermined number of counts will generate a synchronization interrupt signal which resets a counter in each clock to zero. A start subroutine readmits inactive clocks when after a synchronization interrupt signal is generated its counts are within a predetermined readmittance range or its counter counts up to a third predetermined value.

公开(公告)号：US4868814A

公开(公告)日：1989-09-19

申请号：US223453

申请日：1988-07-22

申请人： Semyon Berkovich ,  Henry C. Yee ,  Chris J. Walter

发明人： Semyon Berkovich ,  Henry C. Yee ,  Chris J. Walter

IPC分类号： G06F13/36 ,  H04L12/44

CPC分类号： H04L12/44

摘要： A method and apparatus is described for distributing data in a hierarchically connected system (10) comprising a plurality of nodes (12-25) at each of a plurality of hierarchical levels, one or more bidirectional buses (29-30, 31,32) interconnecting mutually exclusive nodes at each hierarchical level, and a sender (49) for receiving and transmitting data located at each node (12-25) for transmitting and receiving data under the Content Induced Transaction Overlap (CITO) protocol and for transmitting and receiving data without regard to the CITO protocol. Each bidirectional bus (27-32) is interconnected through a node to a node on a bidirectional bus at a higher hierarchical level. Several virtual buses may be formed for distribution of the messages over one or more bidirectional buses (27-33) by controlling the senders (90,92,94,96) at each node by a slot controller (88) which activates the senders (90,92,94,96) as a function of time slot. The invention overcomes the problem of distributing data to all nodes (12-25) in a hierarchically connected system as well as to nodes (14-17 ) at a selected hierarchical level or to nodes (18-19) hierarchically connected subordinate to a node (14).

摘要翻译： 描述了一种用于在分层连接的系统（10）中分发数据的方法和装置，所述系统包括在多个分层级别中的每一个处的多个节点（12-25），一个或多个双向总线（29-30,31,32） 在每个分层级互连互斥节点，以及发送器（49），用于接收和发送位于每个节点（12-25）处的数据，用于在内容诱导事务重叠（CITO）协议下发送和接收数据，并用于发送和接收数据 而不考虑CITO协议。 每个双向总线（27-32）通过一个节点互连到一个更高级别的双向总线上的一个节点。 可以形成几个虚拟总线，用于通过一个时隙控制器（88）控制在每个节点处的发送者（90,92,94,96），从而通过一个或多个双向总线（27-33）分发消息，该时隙控制器激活发送者 90,92,94,96）作为时隙的函数。 本发明克服了将分组数据分发到分层连接的系统中的所有节点（12-25）以及在选定的分层级别的节点（14-17）或从下级分层连接到节点（18-19）的问题 （14）。

公开(公告)号：US5392291A

公开(公告)日：1995-02-21

申请号：US703025

申请日：1991-05-20

申请人： Semyon Berkovich ,  Chris J. Walter ,  Henry C. Yee

发明人： Semyon Berkovich ,  Chris J. Walter ,  Henry C. Yee

IPC分类号： G06F11/00 ,  H04J3/12 ,  H04J15/00

CPC分类号： G06F11/20 ,  G06F11/1423

摘要： A communication method and apparatus incorporating fault-tolerance and increased transmission reliability in a content-induced transaction overlap (CITO) system is disclosed. The system is driven by an error-detecting and correcting CITO-based protocol whereby transient failures are transparent to the user. A parity check is built into the protocol for detecting failures due to hard faults. A redundancy configuration is also disclosed which permits circumvention of fabrication defects, thereby allowing an increased manufacturing yield.

摘要翻译： 公开了一种在内容引发的交易重叠（CITO）系统中结合容错和增加的传输可靠性的通信方法和装置。 该系统由错误检测和校正基于CITO的协议驱动，从而瞬态故障对于用户是透明的。 用于检测由于硬故障引起的故障的协议中内置了奇偶校验。 还公开了冗余配置，其允许规避制造缺陷，从而允许增加的制造产量。

公开(公告)号：US4339723A

公开(公告)日：1982-07-13

申请号：US114795

申请日：1980-01-24

申请人： Henry C. Yee

发明人： Henry C. Yee

IPC分类号： G01R29/027 ,  H04Q9/14 ,  H03K5/22

CPC分类号： G01R29/0273 ,  H04Q9/14

摘要： A pulse width discriminator using a negative logic technique including two monostable multivibrators for generating test pulses and a D-latch for generating an output signal in response to the test pulses indicating that the received signal is of a predetermined length.

摘要翻译： 使用包括用于产生测试脉冲的两个单稳态多谐振荡器的负逻辑技术的脉冲宽度鉴别器和用于响应于指示接收到的信号是预定长度的测试脉冲而产生输出信号的D锁存器。

公开(公告)号：US4311986A

公开(公告)日：1982-01-19

申请号：US942003

申请日：1978-09-13

申请人： Henry C. Yee

发明人： Henry C. Yee

IPC分类号： G01R29/027 ,  G06F13/00 ,  H04Q9/14 ,  H04Q9/00

CPC分类号： G01R29/0273 ,  H04Q9/14

摘要： A single line refigurable power transmission and signal multiplexing system having a central processor and a plurality of remotely located devices such as sensors, actuators and associated interfaces. Communications between the central processor and the remote devices is accomplished via a single bi-directional transmission line. A negative logic pulse width encoding technique is utilized to facilitate power and signal transmission. Selective activation is accomplished by a pulse width discriminator associated with each interface which employs a two-part recognition test to identify specific pulse width signals.

摘要翻译： 具有中央处理器和多个远程定位的设备（诸如传感器，致动器和相关接口）的单线可重复传输和信号复用系统。 中央处理器和远程设备之间的通信通过单个双向传输线实现。 利用负逻辑脉冲宽度编码技术来促进功率和信号传输。 选择性激活通过与每个接口相关联的脉冲宽度鉴别器来实现，该接口采用两部分识别测试来识别特定的脉冲宽度信号。