公开(公告)号：US20190051588A1

公开(公告)日：2019-02-14

申请号：US16165486

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Toshihiro NAKAMURA ,  Isao MOTEGI ,  Noriyuki SHIMAZU ,  Masanobu HIROSE ,  Taro FUKUNAGA

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

公开(公告)号：US20210233902A1

公开(公告)日：2021-07-29

申请号：US17233177

申请日：2021-04-16

Applicant: SOCIONEXT INC.

Inventor： Toshihiro NAKAMURA ,  Taro FUKUNAGA

IPC: H01L27/02 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

公开(公告)号：US20220367442A1

公开(公告)日：2022-11-17

申请号：US17877534

申请日：2022-07-29

Applicant: Socionext Inc.

Inventor： Taro FUKUNAGA ,  Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/02

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.