公开(公告)号：US20220254811A1

公开(公告)日：2022-08-11

申请号：US17730881

申请日：2022-04-27

Applicant: Socionext Inc.

Inventor： Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/118

Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.

公开(公告)号：US20220367442A1

公开(公告)日：2022-11-17

申请号：US17877534

申请日：2022-07-29

Applicant: Socionext Inc.

Inventor： Taro FUKUNAGA ,  Masahisa IIDA ,  Toshihiro NAKAMURA

IPC: H01L27/02

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

公开(公告)号：US20190052259A1

公开(公告)日：2019-02-14

申请号：US16165431

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA

IPC: H03K17/16 ,  H03K17/00 ,  H03K19/0185

Abstract: In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off.

公开(公告)号：US20180287600A1

公开(公告)日：2018-10-04

申请号：US16001199

申请日：2018-06-06

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA ,  Masahiro GION

IPC: H03K17/04 ,  H03K19/017 ,  H03K19/0175 ,  H03K17/687 ,  H03K19/0944

CPC classification number: H03K17/04 ,  H03K17/687 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/018521 ,  H03K19/0944

Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.

公开(公告)号：US20210105009A1

公开(公告)日：2021-04-08

申请号：US17122737

申请日：2020-12-15

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA ,  Masahiro GION

IPC: H03K3/356 ,  H03K19/003 ,  H03K19/0185

Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

公开(公告)号：US20230208407A1

公开(公告)日：2023-06-29

申请号：US18177558

申请日：2023-03-02

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA ,  Masahiro GION

IPC: H03K3/356 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K3/356017 ,  H03K19/00315 ,  H03K19/018507

Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

公开(公告)号：US20240250676A1

公开(公告)日：2024-07-25

申请号：US18627023

申请日：2024-04-04

Applicant: Socionext Inc.

Inventor： Kyota SHIMIZU ,  Tomohiko KOTO ,  Masahisa IIDA

IPC: H03K17/041 ,  H03K19/0185

CPC classification number: H03K17/04106 ,  H03K19/018507

Abstract: An output circuit outputs an output signal having an amplitude VCCH responsive to an input signal having an amplitude VCCL. The output circuit includes: first and second p-type transistors connected in series between VCCH and an output terminal; a first n-type transistor grounded at its source and receiving a first signal at its gate; a third p-type transistor connected to VCCH at its source, connected to the gate of the first p-type transistor at its drain, and receiving a second signal at its gate; and a first diode connected between the drains of the first n-type transistor and the third p-type transistor.

公开(公告)号：US20190081616A1

公开(公告)日：2019-03-14

申请号：US16160238

申请日：2018-10-15

Applicant: SOCIONEXT INC.

Inventor： Masahisa IIDA

IPC: H03K3/012 ,  H03K17/687

CPC classification number: H03K3/012 ,  H03K17/687 ,  H03K19/018521 ,  H03K19/20 ,  H03K2217/0081

Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).