公开(公告)号：US20240355406A1

公开(公告)日：2024-10-24

申请号：US18640912

申请日：2024-04-19

Applicant: Socionext Inc.

Inventor： Tatsushi OTSUKA ,  Yuya SHIGENOBU ,  Tokushi YAMAGUCHI

IPC: G11C29/12 ,  G11C29/00 ,  G11C29/38

CPC classification number: G11C29/1201 ,  G11C29/38 ,  G11C29/76

Abstract: A memory circuit includes: a plurality of memory parts, each of which includes a plurality of first memory cells and a second memory cell that is accessed when one of the first memory cells is defective; a plurality of first memory control parts, each of which is configured to control access to a corresponding one of the plurality of memory parts based on a first access request addressing the corresponding memory part, during a first mode; and a second memory control part shared by the plurality of memory parts, and configured to control access to the plurality of memory parts based on a second access request during a second mode.