公开(公告)号：US20180376157A1

公开(公告)日：2018-12-27

申请号：US16119609

申请日：2018-08-31

Applicant: SOCIONEXT INC.

Inventor： Tatsushi OTSUKA

IPC: H04N19/467 ,  G06T7/174

Abstract: An image processing apparatus receives input of an original image that is divided into at least two partial images in a top-and-bottom direction. The image processing apparatus adds a first line number of dummy screen lines to a top portion of a partial image that is a top portion of the original image. The image processing apparatus adds a second line number of dummy screen lines to a lower portion of a partial image that is a lower portion of the original image. The image processing apparatus uses a z×z encoding process unit and performs an encoding process for each of the partial images to which the dummy screen lines have been added.

公开(公告)号：US20240295973A1

公开(公告)日：2024-09-05

申请号：US18663727

申请日：2024-05-14

Applicant: Socionext Inc.

Inventor： Tatsushi OTSUKA

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0683

Abstract: A memory circuit includes memory groups each of which includes memory cells, and is configured to execute a write operation or a read operation in response to a request signal; memory group controllers each of which is provided for a corresponding one of the memory groups; and a first memory controller configured to output a request signal received from an outside to an adjacent memory group controller, wherein, in a case where an address signal included in the received request signal indicates the corresponding one of the memory groups, said each of the memory group controllers outputs the request signal to the corresponding one of the memory groups, and in a case where the address signal indicates a memory group other than the corresponding one of the memory groups, outputs the request signal to a memory group controller at a succeeding stage.

公开(公告)号：US20240355406A1

公开(公告)日：2024-10-24

申请号：US18640912

申请日：2024-04-19

Applicant: Socionext Inc.

Inventor： Tatsushi OTSUKA ,  Yuya SHIGENOBU ,  Tokushi YAMAGUCHI

IPC: G11C29/12 ,  G11C29/00 ,  G11C29/38

CPC classification number: G11C29/1201 ,  G11C29/38 ,  G11C29/76

Abstract: A memory circuit includes: a plurality of memory parts, each of which includes a plurality of first memory cells and a second memory cell that is accessed when one of the first memory cells is defective; a plurality of first memory control parts, each of which is configured to control access to a corresponding one of the plurality of memory parts based on a first access request addressing the corresponding memory part, during a first mode; and a second memory control part shared by the plurality of memory parts, and configured to control access to the plurality of memory parts based on a second access request during a second mode.