公开(公告)号：US5111434A

公开(公告)日：1992-05-05

申请号：US359128

申请日：1989-05-31

Applicant: Soon-In Cho

Inventor： Soon-In Cho

IPC: G11C11/401 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C11/4091 ,  G11C11/4097

Abstract: A semiconductor DRAM comprising a circuit arrangement in which an undesirable effect due to the coupling capacitance between bit lines thereof can be reduced, comprises: a plurality of bit lines arranged parallel to each other; a plurality of word lines intersecting each plurality of bit lines; a plurality of upper sense amplifiers respectively connected to uppermost ends of each of odd numbered bit line pairs; a plurality of lower sense amplifiers respectively connected to lowermost ends of each of even numbered bit line pairs; a memory cell array having a plurality of memory cells arranged sequentially in a diagonal line within selected locations of a plurality of spacings formed by intersection of the bit lines and word lines, the memory cell being disposed at every fourth spacing in a row and a column; first latching means for activating said upper sense amplifiers, the latching means being connected with said upper sense amplifiers; and second latching means coupled with said lower sense amplifiers, said first latching means and said second latching means being alternately activated to each other.

Abstract translation: 一种包括电路装置的半导体DRAM，其中由于其位线之间的耦合电容引起的不期望的影响可以减小，包括：彼此平行布置的多个位线; 与每个位线相交的多个字线; 分别连接到奇数位线对中的每一个的最上端的多个高级读出放大器; 分别连接到每个偶数位线对的最下端的多个下感测放大器; 存储单元阵列，具有多个存储单元，所述多个存储器单元按照位线和字线的相交形成的多个间隔的选定位置内的对角线顺序排列，所述存储单元以行和列的每隔四行间隔配置 ; 用于激活所述上感测放大器的第一锁存装置，所述锁存装置与所述上感测放大器连接; 以及与所述下感测放大器耦合的第二锁存装置，所述第一锁定装置和所述第二锁定装置彼此交替地被激活。