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1.发明授权Method and system for executing a program within a multiscalar processor by processing linked thread descriptors 失效通过处理链接线程描述符来执行多级数据处理器内程序的方法和系统公开(公告)号：US06212542B1
公开(公告)日：2001-04-03
申请号：US08767487
申请日：1996-12-16
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/30087 , G06F9/3009 , G06F9/3851
摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.
摘要翻译： 提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。 多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。 多个线程中的每一个具有单个入口点和多个可能的出口点。 多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。 根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。 与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构 。 第三线程被分配给用于执行的多个处理元件中的所选择的一个。 在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。 响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。
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2.发明授权Method and system for constructing a program including a navigation instruction 失效用于构建包括导航指令的程序的方法和系统
公开(公告)号：US5887166A
公开(公告)日：1999-03-23
申请号：US767491
申请日：1996-12-16
CPC分类号： G06F9/4881
摘要： A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.
摘要翻译： 提供了一种方法和系统，用于构建可由包括用于执行线程的一个或多个处理元件和用于将线程分配给处理元件以执行的线程调度器的处理器执行的程序。 根据该方法，提供多个线程，每个线程包括至少一个控制流程指令。 从多个线程内的一个或多个控制流程指令，确定特定线程的执行所依赖的状态。 响应于该确定，创建可由线程调度器执行的至少一个导航指令，其指示将特定线程分配给响应于条件执行的一个处理元件。
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3.发明授权Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution 失效在执行期间在指令流内动态插入辅助指令的处理器和方法
公开(公告)号：US5961639A
公开(公告)日：1999-10-05
申请号：US767492
申请日：1996-12-16
CPC分类号： G06F9/4881 , G06F9/30087 , G06F9/3009 , G06F9/30185 , G06F9/3822 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857
摘要： A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones of the plurality of program instructions is supplied to the processor. In response to the processor processing a program instruction within the instruction stream that has an associated auxiliary instruction within the set of auxiliary instructions, the associated auxiliary instruction is automatically inserted within the instruction stream and the associated auxiliary instruction is executed within the processor.
摘要翻译： 提供了一种在处理器内执行程序的处理器和方法。 根据该方法，存储包括程序和一组辅助指令的多个程序指令。 包括多个程序指令中的选择的指令流被提供给处理器。 响应于处理器处理在辅助指令集合内具有相关联的辅助指令的指令流内的程序指令，相关联的辅助指令被自动插入指令流中，并且在处理器内执行相关联的辅助指令。
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4.发明申请公开(公告)号：US20110107146A1
公开(公告)日：2011-05-05
申请号：US12611156
申请日：2009-11-03
IPC分类号： G06F11/263 , G06F11/28
CPC分类号： G06F11/24
摘要： A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
摘要翻译： 测试系统收集传递的事件数据和失败的事件数据，并将收集的数据分别合并到通过的子序列和失败的子序列中。 测试系统识别在时间片和跟踪点片段之间的传递子序列和故障子序列之间的重叠区域，并且使用与重叠区域相对应的事件数据来创建传递事务和失败事务。 接下来，测试系统相对于第二故障事务相对于第一故障事务来检测第一传递事务之间相对于第二传递事务的定时差异。 测试系统然后报告检测到的定时差异，这允许测试工程师干扰测试程序，以便更频繁地捕获由异步定时条件引起的间歇性故障。
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5.发明授权公开(公告)号：US08234618B2
公开(公告)日：2012-07-31
申请号：US12611156
申请日：2009-11-03
CPC分类号： G06F11/24
摘要： A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
摘要翻译： 测试系统收集传递的事件数据和失败的事件数据，并将收集的数据分别合并到通过的子序列和失败的子序列中。 测试系统识别在时间片和跟踪点片段之间的传递子序列和故障子序列之间的重叠区域，并且使用与重叠区域相对应的事件数据来创建传递事务和失败事务。 接下来，测试系统相对于第二故障事务相对于第一故障事务来检测第一传递事务之间相对于第二传递事务的定时差异。 测试系统然后报告检测到的定时差异，这允许测试工程师干扰测试程序，以便更频繁地捕获由异步定时条件引起的间歇性故障。
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