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    MULTI-PASS SOFT PROGRAMMING
    1.
    发明申请
    MULTI-PASS SOFT PROGRAMMING 有权
    多通软件编程

    公开(公告)号：US20150103601A1

    公开(公告)日：2015-04-16

    申请号：US14050490

    申请日：2013-10-10

    申请人： Spansion LLC

    发明人： Gulzar A. KATHAWALA ,  Mark W. RANDOLPH ,  Yi HE ,  Zhizheng LIU ,  Tio Wei NEO ,  Cindy SUN ,  Shivananda SHETTY ,  Phuog BANH ,  Richard FASTOW ,  Loi LA ,  Harry Hao KUO

    IPC分类号： G11C16/12 ,  G11C16/34

    CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3459

    摘要： Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

    摘要翻译： 这里公开了用于利用软编程非易失性存储器的系统，方法和计算机程序产品实施例。 实施例通过对在第一阶段中软编程验证失败的非易失性存储器中的每个字线向所有存储器单元顺序施加单个软编程电压脉冲来操作。 第一阶段中单个软编程电压脉冲的这种顺序应用可以重复预定次数或直到满足阈值。 一旦预定次数完成或者阈值被满足，则软编程进行到第二阶段，其中软编程保留在每个字线上，直到沿着字线的所有存储单元通过软编程验证。

    APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
    2.
    发明申请
    APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS 审中-公开
    减少位线干扰的装置和方法

    公开(公告)号：US20140233339A1

    公开(公告)日：2014-08-21

    申请号：US13769403

    申请日：2013-02-18

    申请人： SPANSION LLC.

    发明人： Amichai GIVANT ,  Ilan BLOOM ,  Mark RANDOLPH ,  Zhizheng LIU

    IPC分类号： G11C8/08

    CPC分类号： G11C8/08 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0416 ,  G11C16/0475 ,  G11C16/08 ,  G11C29/06

    摘要： A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.

    摘要翻译： 一种非易失性存储器件，包括存储单元阵列，该存储单元阵列包括以行和列排列的多个非易失性存储器单元，其中布置在同一行中的存储单元共享字线，并且布置在同一列中的存储器单元共享位线 ; 以及至少一个地址解码器，当沿着共享位线提供编程或擦除电压时，向所述阵列中的至少一个非访问字线提供负电压。