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公开(公告)号：US06631006B2
公开(公告)日：2003-10-07
申请号：US09861231
申请日：2001-05-17
IPC分类号： G01B1114
CPC分类号： B23D47/042 , B23D59/001 , B23D59/008
摘要： A marking assembly for marking feature locations of a material and an automated processing system that uses input from the marking assembly to process the material. Feature locations such as defect positions and the size of the material are measured with an optical measuring device. The optical measuring device sends and receives light along a light path that is substantially parallel to a processing dimension of the material. A user manually interrupts the light path at a feature location, sending light from the feature location to the optical measuring device. The optical measuring device measures the feature location from the light received from the feature location and sends the feature location to a processor. The processor automatically positions the material relative to a modifying device, based on the feature location.
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公开(公告)号：US07076710B2
公开(公告)日：2006-07-11
申请号：US10413613
申请日：2003-04-14
IPC分类号： G01R31/28
CPC分类号： G11C29/20 , G11C29/14 , G11C2029/0405 , G11C2029/3602
摘要： Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.
摘要翻译： 用于测试具有不均匀二进制地址空间的存储器阵列的方法和系统。 测试系统包括用于产生存储器阵列的地址并用于产生和应用数据模式到存储器阵列的测试引擎。 测试引擎具有包括线性寄存器和用于产生不均匀地址的二进制计数器的串联组合的地址生成器。
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公开(公告)号：US07073105B2
公开(公告)日：2006-07-04
申请号：US10413614
申请日：2003-04-14
CPC分类号： G11C29/20 , G11C29/16 , G11C2029/0405 , G11C2029/3602
摘要： An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array. The comparator compares the data inputted to the data input ports of the memory array from the data control subsystem with the data outputted from the data output ports of the memory array.
摘要翻译： 阵列内置的片上自检系统，用于测试存储器阵列和测试存储器阵列的方法。 存储器阵列具有数据输入端口，数据输出端口和地址端口，以及数据控制子系统，地址控制子系统和比较器。 数据控制子系统生成并将确定性数据模式应用于存储器阵列的数据输入端口。 地址控制子系统与所述数据控制子系统一起生成用于应用于存储器阵列的地址，并且包括序列计数器，用于序列控制器的计数速率控制器，用于控制每个地址的周期数的计数速率控制器分频器 地址控制器以提供地址的精细控制，以及从序列计数器和地址控制器接收输入的X-OR门，X-OR门将地址位输出到存储器阵列。 比较器将从数据控制子系统输入到存储器阵列的数据输入端口的数据与从存储器阵列的数据输出端口输出的数据进行比较。
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4.发明授权公开(公告)号：US06549438B2
公开(公告)日：2003-04-15
申请号：US09845718
申请日：2001-04-30
申请人： Douglas J. Malone
发明人： Douglas J. Malone
IPC分类号： H02M7217
摘要： An AC-to-DC converter furnishing a regulated DC-output voltage from an AC-input supply voltage which is converted with a rectifier that utilizes, in at least two of its legs, IGBT (insulated gate bipolar transistor) devices, preferably of the kind that have no internal diodes. Also included in the converter of this convention is circuitry which tracks zero-crossing events relative to AC-input voltage for the purpose of establishing switching signals and times for such signals for operating the IGBT devices, and wherein thorough-safe operation is associated with malfunctioning of the zero-crossing tracking subcircuitry whereby a failure in that circuitry will result effectively in a shut down of the entire converter, and a bleed down to zero of DC-output voltage.
摘要翻译： 一种AC-DC转换器，其从AC输入电源电压提供稳定的DC输出电压，该AC电压由整流器转换，该整流器在其至少两条支路中使用IGBT（绝缘栅双极晶体管）器件，优选地为 没有内部二极管。 该惯例的转换器还包括跟踪交流输入电压的过零事件的电路，以建立用于操作IGBT器件的这种信号的开关信号和时间，并且其中彻底安全的操作与故障相关 的过零跟踪子电路，由此该电路中的故障将有效地导致整个转换器的关断，并且直流输出电压的下降到零。
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公开(公告)号：US4237374A
公开(公告)日：1980-12-02
申请号：US30296
申请日：1979-04-16
申请人： Douglas J. Malone
发明人： Douglas J. Malone
CPC分类号： H03K21/023 , H03K17/97
摘要： A cutting cylinder of a newspaper press assembly has a magnet member mounted thereon. A semiconductor Hall effect pickoff is mounted in proximity to the cutting cylinder such that the magnet passes by this sensor in close proximity thereto once during each rotation of the cylinder. The output of the Hall effect sensor, which is in the form of pulses, is fed both to a non-inverting and an inverting amplifier. The outputs of the amplifiers are fed to a differential detector which provides an output only in accordance with the difference between the inputs fed thereto, thus eliminating common-mode inputs such as noise signals. The output of the differential detector is fed to a digital counter which provides a count of the input pulses representing the number of newspapers or the like detected by the sensor. The output of the digital counter in turn is fed to a readout device which provides a suitable readout of this count which may be in the form of a display.
摘要翻译： 报纸印刷机组的切割滚筒具有安装在其上的磁性部件。 半导体霍尔效应传感器安装在切割圆筒附近，使得磁体在气缸的每次旋转期间通过该传感器紧邻其一次。 以脉冲形式的霍尔效应传感器的输出被馈送到非反相放大器和反相放大器。 放大器的输出被馈送到差分检测器，该差分检测器仅根据馈送到其的输入之间的差异提供输出，从而消除诸如噪声信号的共模输入。 差分检测器的输出被馈送到数字计数器，数字计数器提供表示由传感器检测到的报纸数量等的输入脉冲的计数。 数字计数器的输出依次被馈送到读出装置，该读出装置提供可能以显示器形式的该计数的适当读出。
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