公开(公告)号：US07073105B2

公开(公告)日：2006-07-04

申请号：US10413614

申请日：2003-04-14

申请人： Thomas J. Knips ,  James W. Dawson ,  John D. Davis ,  Douglas J. Malone

发明人： Thomas J. Knips ,  James W. Dawson ,  John D. Davis ,  Douglas J. Malone

IPC分类号： G11C29/00 ,  G06F12/00

CPC分类号： G11C29/20 ,  G11C29/16 ,  G11C2029/0405 ,  G11C2029/3602

摘要： An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array. The comparator compares the data inputted to the data input ports of the memory array from the data control subsystem with the data outputted from the data output ports of the memory array.

摘要翻译： 阵列内置的片上自检系统，用于测试存储器阵列和测试存储器阵列的方法。 存储器阵列具有数据输入端口，数据输出端口和地址端口，以及数据控制子系统，地址控制子系统和比较器。 数据控制子系统生成并将确定性数据模式应用于存储器阵列的数据输入端口。 地址控制子系统与所述数据控制子系统一起生成用于应用于存储器阵列的地址，并且包括序列计数器，用于序列控制器的计数速率控制器，用于控制每个地址的周期数的计数速率控制器分频器 地址控制器以提供地址的精细控制，以及从序列计数器和地址控制器接收输入的X-OR门，X-OR门将地址位输出到存储器阵列。 比较器将从数据控制子系统输入到存储器阵列的数据输入端口的数据与从存储器阵列的数据输出端口输出的数据进行比较。

公开(公告)号：US07210084B2

公开(公告)日：2007-04-24

申请号：US10413612

申请日：2003-04-14

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

IPC分类号： G11C29/30 ,  G11C29/24

CPC分类号： G11C29/40 ,  G11C11/41

摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

摘要翻译： 具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。 该装置包括NORs在一起的两个子系统。 第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。 第二子系统进一步接收ABIST控制逻辑作为输入：（a）。 组合数组有效位​​标签有效输入以产生有效输出，或（b）将数组有效位​​与标签有效输入进行比较。 该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

公开(公告)号：US07009895B2

公开(公告)日：2006-03-07

申请号：US10814719

申请日：2004-03-31

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/806 ,  G11C29/848

摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.

摘要翻译： 所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。 实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。 为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。 为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。 如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。 然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。 这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。

公开(公告)号：US06584023B1

公开(公告)日：2003-06-24

申请号：US10043024

申请日：2002-01-09

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/848

摘要： An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit. The system also includes programmable logic in communication with the field control signal multiplexor, the spare control signal multiplexor, the data multiplexor and the spare data multiplexor to cause the steer around to take place in response to detecting a defective data bit in the array.

摘要翻译： 本发明的示例性实施例是用于对具有跨越多个数据位的控制的阵列实现列冗余方案的系统。 该系统包括用于接收数据输入的数据位阵列，备用数据位和场控制输入线。 还包括在系统中的电路是将场​​控制信号与场控制输入线分离成一个或多个单独的控制信号，用于激活阵列中相应的数据位或输入到多路复用器。 该系统还包括用于控制阵列中的有缺陷的数据位的电路。 该电路包括：对应于每个场控制信号的场控制信号多路复用器; 备用控制信号多路复用器，用于激活备用数据位; 与阵列中的每个数据位相对应的数据多路复用器; 以及备用数据多路复用器，以将数据输入中的一个引导到备用数据位。 该系统还包括与现场控制信号多路复用器，备用控制信号多路复用器，数据多路复用器和备用数据多路复用器通信的可编程逻辑，以响应于检测到阵列中的有缺陷的数据位而引起转向。

公开(公告)号：US07088638B1

公开(公告)日：2006-08-08

申请号：US11054176

申请日：2005-02-09

申请人： Paul A. Bunce ,  John D. Davis ,  James W. Dawson ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  James W. Dawson ,  Donald W. Plass

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供全局和本地读取控制同步方法和系统。 解码地址信号以基于子阵列选择信号和累积子阵列选择信号来激活。 每当子阵列选择信号变为有效时，累积子阵列选择信号变为有效，因此累积子阵列选择信号的每个脉冲与子阵列选择信号的一个脉冲同步。 使用子阵列选择信号获得用于多个存储器子阵列的本地读取控制信号，并且使用累积子阵列选择信号获得用于存储器阵列的至少一个全局读取控制信号。 在一个示例中，存储器阵列具有分层位线架构。

公开(公告)号：US20140348611A1

公开(公告)日：2014-11-27

申请号：US14283198

申请日：2014-05-20

申请人： John D. Davis

发明人： John D. Davis

IPC分类号： F16B39/12

CPC分类号： F16B43/02 ,  F16B39/10

摘要： A jackscrew nut and/or bolt head assembly includes a bottom washer that is interlocked via circumferentially arrayed castle extensions and recesses. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary pre tightening torque exerted onto the main body of the nut and/or bolt head via a tool that concurrently accesses all jackscrew heads extending above the main body. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced. The jackscrews are thinned in reverse for maximum contact area at their spherical bottoms.

摘要翻译： 螺旋螺母和/或螺栓头组件包括底部垫圈，其通过周向排列的城堡延伸部和凹部互锁。 因此，垫圈顶部的球形面保持与对应的球形顶螺旋底座对准，这保证了在起重螺旋桨装载期间的角度之前的弹性起重螺丝刀位移期间的均匀分布的接触压力。 底部垫圈联锁装置可以进一步提供通过同时访问在主体上方延伸的所有顶螺旋头的工具传递施加到螺母和/或螺栓头主体上的初级预紧力矩。 组件可以首先通过主扭矩紧固，从而大大减少次级起重螺丝起子和排量。 在其球形底部的最大接触面积处，顶针螺纹相反地变薄。

公开(公告)号：US20130054936A1

公开(公告)日：2013-02-28

申请号：US13218480

申请日：2011-08-26

申请人： John D. Davis

发明人： John D. Davis

IPC分类号： G06F12/12 ,  G06F12/10

CPC分类号： G11C29/76 ,  G11C13/0004

摘要： Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.

摘要翻译： 不可操作的位在存储器块中确定。 不是将块放弃为不可操作，而是生成包括至少一个存储器页指针的数据结构，该存储器页指针标识存储器块中的不可操作位的位置。 数据结构存储在为数据结构保留的一组存储块中。 指向数据结构的指针存储在与不可操作的位相关联的与存储器块相关联的元数据中。 当对于存储器块接收到较后的存储器操作时，从元数据中检索指针，并且使用存储器页指针来避免不可操作的位。

公开(公告)号：US08345497B2

公开(公告)日：2013-01-01

申请号：US12822058

申请日：2010-06-23

申请人： Paul A. Bunce ,  John D. Davis ,  Diana M. Henderson ,  Jigar J. Vora

发明人： Paul A. Bunce ,  John D. Davis ,  Diana M. Henderson ,  Jigar J. Vora

IPC分类号： G11C7/00

CPC分类号： G11C16/02 ,  G11C7/1048 ,  G11C11/413 ,  G11C2207/002

摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.

摘要翻译： 用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制 信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

公开(公告)号：US20120110278A1

公开(公告)日：2012-05-03

申请号：US12915025

申请日：2010-10-29

申请人： John D. Davis ,  Karin Strauss ,  Douglas C. Burger

发明人： John D. Davis ,  Karin Strauss ,  Douglas C. Burger

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2024 ,  G11C13/0004 ,  G11C13/0035 ,  G11C29/76

摘要： Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table.

摘要翻译： PCM设备中的不可操作的相变存储器（PCM）块被重新映射到一个或多个可操作的PCM块，例如。 通过维护不可操作的块表，其包括每个不可操作的PCM块的条目和重新映射的PCM块的地址。 或者，可以通过将重映射块的地址存储在块本身中来重新映射PCM块，并且设置指示块的重映射比特已被重新映射。 在由处理器执行重新映射的情况下，可以在转换旁边的缓冲器中设置不可操作的块位，缓冲器指示虚拟存储器页是否与不可操作或重新映射的PCM块相关联。 当接收到访问虚拟存储器页面的请求时，处理器引用与虚拟存储器页面相关联的不可操作块位，以确定是否检查不可操作块表中的重新映射的PCM块。

公开(公告)号：US08102559B2

公开(公告)日：2012-01-24

申请号：US11549372

申请日：2006-10-13

申请人： John D. Davis ,  Rickey M. Fullmer ,  Michael S. Lafranzo ,  Richard L. Lenski ,  Charles J. Novak, Jr.

发明人： John D. Davis ,  Rickey M. Fullmer ,  Michael S. Lafranzo ,  Richard L. Lenski ,  Charles J. Novak, Jr.

IPC分类号： G06K15/00

CPC分类号： B41F33/0009 ,  B41F31/045 ,  B41F33/0045 ,  B41F33/0054 ,  B41F33/02 ,  B41P2233/11 ,  B41P2233/12

摘要： A system and method for accurately controlling a printing process regardless web width or printing layout. A user interface is provided for configuring a printing application that includes a plurality of sensors arranged to form an interface region. The sensors are configured to generate feedback indicating user interaction with the interface region. A controller is configured to map the plurality of sensors into virtual keys based on at least a columniation of the printing application and adjust parameters of the printing application based on the feedback.

摘要翻译： 一种无论幅宽或印刷布局精确控制印刷过程的系统和方法。 提供了用于配置包括布置成形成接口区域的多个传感器的打印应用的用户界面。 传感器被配置为产生指示与接口区域的用户交互的反馈。 控制器被配置为基于打印应用的至少一个列分列将多个传感器映射到虚拟键中，并且基于该反馈来调整打印应用的参数。