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    ABIST data compression and serialization for memory built-in self test of SRAM with redundancy
    2.
    发明授权
    ABIST data compression and serialization for memory built-in self test of SRAM with redundancy 失效
    ABIST数据压缩和串行化用于内存具有冗余的SRAM自检

    公开(公告)号：US07380191B2

    公开(公告)日：2008-05-27

    申请号：US11054566

    申请日：2005-02-09

    申请人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    发明人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    IPC分类号： G01R31/28 ,  G01C29/00

    CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C29/40 ,  G11C29/48 ,  G11C29/802 ,  G11C2029/3602

    摘要： A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.

    摘要翻译： 一种实现ABIST数据压缩和串行化的方法和装置，用于具有冗余的SRAM的内存自检。 该方法包括提供为一个故障数据输出断言的检测信号，两个故障数据输出和大于两个故障数据输出。 该方法还包括用对应的二进制表示值来单独编码每个相应的故障数据输出的故障位位置。 该方法还包括串行化提供检测信号和单独编码的结果，并将序列化的结果发送到单个故障总线上的冗余支持寄存器功能。

    Integrated system logic and ABIST data compression for an SRAM directory
    3.
    发明授权
    Integrated system logic and ABIST data compression for an SRAM directory 失效
    用于SRAM目录的集成系统逻辑和ABIST数据压缩

    公开(公告)号：US07210084B2

    公开(公告)日：2007-04-24

    申请号：US10413612

    申请日：2003-04-14

    申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

    发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

    IPC分类号： G11C29/30 ,  G11C29/24

    CPC分类号： G11C29/40 ,  G11C11/41

    摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

    摘要翻译： 具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。 该装置包括NORs在一起的两个子系统。 第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。 第二子系统进一步接收ABIST控制逻辑作为输入：（a）。 组合数组有效位​​标签有效输入以产生有效输出，或（b）将数组有效位​​与标签有效输入进行比较。 该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

    Method for self-correcting cache using line delete, data logging, and fuse repair correction
    4.
    发明授权
    Method for self-correcting cache using line delete, data logging, and fuse repair correction 有权
    使用行删除，数据记录和保险丝修复校正自校正缓存的方法

    公开(公告)号：US07529997B2

    公开(公告)日：2009-05-05

    申请号：US11079816

    申请日：2005-03-14

    申请人： Patrick J. Meaney ,  William V. Huott ,  Thomas J. Knips ,  David J. Lund ,  Bryan L. Mechtly ,  Pradip Patel

    发明人： Patrick J. Meaney ,  William V. Huott ,  Thomas J. Knips ,  David J. Lund ,  Bryan L. Mechtly ,  Pradip Patel

    IPC分类号： G01R31/28

    CPC分类号： G11C29/44 ,  G11C11/41 ,  G11C15/00 ,  G11C29/4401 ,  G11C29/789 ,  G11C2029/0407 ,  G11C2029/1208

    摘要： An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.

    摘要翻译： 一种用于保护计算机系统免受阵列可靠性故障的装置和方法使用阵列内置自检逻辑以及代码和硬件来删除有缺陷的高速缓存行或集合，识别相应的保险丝修复值，如果备用保险丝为主动式，则主动呼叫家庭 不可用，为下一次重新启动计划软保险丝修复，下次重新启动时计划行删除，在表中存储删除和保险丝修复（标记为电子序列号，删除时间戳或ABIST失败事件，地址和故障类型 ），并且如果有任何未被记录的遗漏的删除事件，则主动呼叫回家。 保险丝信息也可以更加永久地存储在硬件电子保险丝和/或EPROM中。 在重新启动期间，以前的修复可以应用于机器，以便ABIST将成功运行，以前的删除将通过检查进行维护，以允许由删除行保护的一些ABIST故障通过。

    Non-binary address generation for ABIST
    5.
    发明授权
    Non-binary address generation for ABIST 失效
    ABIST的非二进制地址生成

    公开(公告)号：US07076710B2

    公开(公告)日：2006-07-11

    申请号：US10413613

    申请日：2003-04-14

    申请人： Thomas J. Knips ,  Tom Y. Chang ,  James W. Dawson ,  Douglas J. Malone

    发明人： Thomas J. Knips ,  Tom Y. Chang ,  James W. Dawson ,  Douglas J. Malone

    IPC分类号： G01R31/28

    CPC分类号： G11C29/20 ,  G11C29/14 ,  G11C2029/0405 ,  G11C2029/3602

    摘要： Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.

    摘要翻译： 用于测试具有不均匀二进制地址空间的存储器阵列的方法和系统。 测试系统包括用于产生存储器阵列的地址并用于产生和应用数据模式到存储器阵列的测试引擎。 测试引擎具有包括线性寄存器和用于产生不均匀地址的二进制计数器的串联组合的地址生成器。

    Apparatus and method for implementing multiple memory redundancy with delay tracking clock
    6.
    发明授权
    Apparatus and method for implementing multiple memory redundancy with delay tracking clock 失效
    用延迟跟踪时钟实现多重存储冗余的装置和方法

    公开(公告)号：US07068554B1

    公开(公告)日：2006-06-27

    申请号：US11054272

    申请日：2005-02-09

    申请人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    发明人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    IPC分类号： G11C7/00

    CPC分类号： G11C29/842

    摘要： A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.

    摘要翻译： 存储器冗余控制装置包括静态比较级，其被配置为将请求的存储器地址的比特与表示缺陷存储器地址的相应的熔丝信息比特进行比较。 动态级被配置为接收静态比较级的输出，动态级的输出被预充电，以便最初去激活主子阵列解码电路。 动态级由其时钟信号进一步触发。 在激活时钟信号时，只要在请求的存储器地址和有缺陷的存储器地址之间存在匹配时，动态级的输出保持预充电，并且只要所请求的存储器地址和存储器地址之间存在不匹配，则动态级的输出被放电 有缺陷的内存地址。 延迟跟踪时钟发生器被配置为相对于动态级产生延迟跟踪时钟信号，以将动态级的输出门控到备用子阵列解码电路，其中每当动态级的输出被激活时，备用子阵列解码电路被激活 在激活时钟信号后仍保持预充电。

    Method and apparatus for ABIST diagnostics
    8.
    发明授权
    Method and apparatus for ABIST diagnostics 失效
    用于ABIST诊断的方法和装置

    公开(公告)号：US07076706B2

    公开(公告)日：2006-07-11

    申请号：US09841569

    申请日：2001-04-24

    申请人： Joseph E. Eckelman ,  Thomas J. Knips

    发明人： Joseph E. Eckelman ,  Thomas J. Knips

    IPC分类号： G01R31/28

    CPC分类号： G06F11/263

    摘要： A method for real time capture of the desired failing chip cell diagnostic information from high speed testing of a semiconductor chip with on chip LSSD registers having built in self test functions and a fail trap register, and there is provided a programmable skip fail counter, and a hold and compare function circuit. The programmable skip counter is enabled for initialization to a “record first fail” mode, and then with non-zero values of the skip counter to a “record next fail” mode with scan initialization of the LSSD registers of the semiconductor chip. The diagnostic information for the chip is obtained by collecting data from scanning the circuits of said semiconductor chip for a failing cell for immediate scan-out off-chip at a level of assembly test.

    摘要翻译： 一种用于通过具有内置自检功能的片上LSSD寄存器和故障陷阱寄存器的半导体芯片的高速测试来实时捕获所需故障芯片单元诊断信息的方法，并且提供了可编程跳过失败计数器，以及 一个保持和比较功能电路。 可编程跳过计数器用于初始化为“记录第一失败”模式，然后将跳过计数器的非零值设置为具有半导体芯片的LSSD寄存器的扫描初始化的“记录下一个故障”模式。 芯片的诊断信息是通过在组装测试的水平上收集来自扫描半导体芯片的电路的数据，用于在片外立即扫描的故障单元。

    Method and apparatus for implementing multiple column redundancy for memory
    9.
    发明授权
    Method and apparatus for implementing multiple column redundancy for memory 有权
    用于为存储器实现多列冗余的方法和装置

    公开(公告)号：US07064990B1

    公开(公告)日：2006-06-20

    申请号：US11053812

    申请日：2005-02-09

    申请人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    发明人： James W. Dawson ,  Thomas J. Knips ,  Donald W. Plass ,  Kenneth J. Reyer

    IPC分类号： G11C7/00

    CPC分类号： G11C29/848

    摘要： An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.

    摘要翻译： 用于在单个存储器阵列内实现多个存储器列冗余的装置包括内部划分为至少一对子列元素的多个存储器阵列元件。 至少一个备用存储器元件被配置为与子列元素之一对应的大小。 配置输入冗余多路复用级和输出冗余多路复用级用于围绕一个或多个有缺陷的存储器阵列元件转向，并且输入位解码级和输出位解码级用于实现相对于 输入冗余复用级和输出冗余复用级。