公开(公告)号：US06971038B2

公开(公告)日：2005-11-29

申请号：US10061695

申请日：2002-02-01

申请人： Sribalan Santhanam ,  Vincent R. von Kaenel ,  David A. Kruckemyer

发明人： Sribalan Santhanam ,  Vincent R. von Kaenel ,  David A. Kruckemyer

IPC分类号： G06F1/08 ,  G06F1/10 ,  G06F1/32

CPC分类号： G06F1/08 ,  G06F1/10

摘要： A processor may include an execution circuit, an issue circuit coupled to the execution circuit, and a clock tree for clocking circuitry in the processor. The issue circuit issues an instruction to the execution circuit, and generates a control signal responsive to whether or not the instruction is issued to the execution circuit. The execution circuit includes at least a first subcircuit and a second subcircuit. A portion of the clock tree supplies a plurality of clocks to the execution circuit, including at least a first clock clocking the first subcircuit and at least a second clock clocking the second subcircuit. The portion of the clock tree is coupled to receive the control signal for collectively conditionally gating the plurality of clock, and is also configured to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit. A system on a chip may include several processors, and one or more of the processors may be conditionally clocked at the processor level.

摘要翻译： 处理器可以包括执行电路，耦合到执行电路的发行电路，以及用于在处理器中计时电路的时钟树。 发行电路向执行电路发出指令，并且响应于是否向执行电路发出指令而生成控制信号。 执行电路至少包括第一子电路和第二子电路。 时钟树的一部分向执行电路提供多个时钟，包括至少第一时钟计时第一分支电路和至少第二时钟计时第二分支电路。 时钟树的部分被耦合以接收控制信号，用于共同有条件地选通多个时钟，并且还被配置为响应于执行电路的相应子电路中的活动而单独有条件地选择多个时钟中的至少一些。 芯片上的系统可以包括几个处理器，并且一个或多个处理器可以在处理器级别有条件地定时。

公开(公告)号：US07355905B2

公开(公告)日：2008-04-08

申请号：US11173565

申请日：2005-07-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US07760559B2

公开(公告)日：2010-07-20

申请号：US12325476

申请日：2008-12-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US08416635B2

公开(公告)日：2013-04-09

申请号：US13617344

申请日：2012-09-14

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US20130016575A1

公开(公告)日：2013-01-17

申请号：US13617344

申请日：2012-09-14

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US08098534B2

公开(公告)日：2012-01-17

申请号：US12791080

申请日：2010-06-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20110235442A1

公开(公告)日：2011-09-29

申请号：US13155097

申请日：2011-06-07

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20100238745A1

公开(公告)日：2010-09-23

申请号：US12791080

申请日：2010-06-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US08289785B2

公开(公告)日：2012-10-16

申请号：US13155097

申请日：2011-06-07

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US20090080268A1

公开(公告)日：2009-03-26

申请号：US12325476

申请日：2008-12-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。