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公开(公告)号：US20090170256A1
公开(公告)日：2009-07-02
申请号：US12206456
申请日：2008-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/268 , H01L21/2686 , H01L21/324 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.
摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。
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公开(公告)号：US07129127B2
公开(公告)日：2006-10-31
申请号：US10950138
申请日：2004-09-24
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.
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公开(公告)号：US20080064175A1
公开(公告)日：2008-03-13
申请号：US11940433
申请日：2007-11-15
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。 或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410。 而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。
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公开(公告)号：US09048180B2
公开(公告)日：2015-06-02
申请号：US11383721
申请日：2006-05-16
IPC分类号： H01L21/02 , H01L21/265 , H01L21/318 , H01L21/324 , H01L29/66
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410 而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。
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公开(公告)号：US20080277699A1
公开(公告)日：2008-11-13
申请号：US11747708
申请日：2007-05-11
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译： 一种PMOS晶体管及其制造方法。 该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。 原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且具有在半导体晶片的表面处具有最大宽度的外延SiGe区域。
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公开(公告)号：US07112516B2
公开(公告)日：2006-09-26
申请号：US10677614
申请日：2003-10-02
IPC分类号： H01L21/22
CPC分类号： H01L21/2255
摘要： One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底内形成P-N结的方法。 该方法包括在主要掺杂剂例如硼的固体源扩散之前在半导体晶体矩阵内提供临时杂质物质，例如氟。 杂质原子相对于硅原子是更快的扩散物质。 在扩散期间，临时杂质物质用于减小初级掺杂剂扩散的深度，从而有助于形成非常浅的结。
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公开(公告)号：US07786518B2
公开(公告)日：2010-08-31
申请号：US12212346
申请日：2008-09-17
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.
摘要翻译： 提供半导体器件和制造方法，其中一次性栅极形成在隔离区域上。 包括一次性侧壁结构的侧壁结构形成在一次性门的侧壁上。 外延生长的硅锗形成在由侧壁限定的凹部中。 该方法在器件中提供压缩应变通道，而不会外延生长的硅锗的面。
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公开(公告)号：US07553717B2
公开(公告)日：2009-06-30
申请号：US11747708
申请日：2007-05-11
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译： 一种PMOS晶体管及其制造方法。 该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。 原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且在半导体晶片的表面具有最大宽度的外延SiGe区域。
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公开(公告)号：US06852603B2
公开(公告)日：2005-02-08
申请号：US10677610
申请日：2003-10-02
IPC分类号： H01L21/225 , H01L21/331
CPC分类号： H01L21/2255
摘要： One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底内形成P-N结的方法。 该方法包括在主要掺杂剂例如硼的固体源扩散之前在半导体晶体矩阵内提供临时杂质物质，例如氟。 杂质原子相对于硅原子是更快的扩散物质。 在扩散期间，临时杂质物质用于减小初级掺杂剂扩散的深度，从而有助于形成非常浅的结。
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公开(公告)号：US07994073B2
公开(公告)日：2011-08-09
申请号：US11940433
申请日：2007-11-15
IPC分类号： H01L21/31
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。 或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410.而且，用于制造具有低应力牺牲帽层120,410的晶体管40,400的方法300,500。
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