Reducing processing bias in a soft forward error correction (FEC) decoder
    1.
    发明授权
    Reducing processing bias in a soft forward error correction (FEC) decoder 有权
    降低软前向纠错(FEC)解码器中的处理偏差

    公开(公告)号:US08631305B2

    公开(公告)日:2014-01-14

    申请号:US13435823

    申请日:2012-03-30

    IPC分类号: H03M13/00

    CPC分类号: H04B10/00 H04L1/0045

    摘要: A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.

    摘要翻译: 系统被配置为接收包括一组样本的单词; 随机选择样本的一个子集; 从子集中识别具有最低可靠性水平的第一个样本; 选择样品的另一个子集; 从另一个子集中识别具有最低可靠性水平的第二个样本; 并基于所选择的第一样本和所选择的第二样本创建合并的子集。 该系统还被配置为选择样本的另一子集; 从另一个子集中确定具有最低可靠性水平的第三个样本; 从合并的子集中确定与最低可靠性相关联的第四个样本; 基于第四个样本比第三个样本包含在另一个合并子集中更大的概率,创建另一个合并子集; 并根据来自其他合并子集的样本生成另一个单词; 并使用其他单词处理单词。

    REDUCING PROCESSING BIAS IN A SOFT FORWARD ERROR CORRECTION (FEC) DECODER
    2.
    发明申请
    REDUCING PROCESSING BIAS IN A SOFT FORWARD ERROR CORRECTION (FEC) DECODER 有权
    在软前向纠错(FEC)解码器中减少处理偏差

    公开(公告)号:US20130259492A1

    公开(公告)日:2013-10-03

    申请号:US13435823

    申请日:2012-03-30

    IPC分类号: H04B10/06

    CPC分类号: H04B10/00 H04L1/0045

    摘要: A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.

    摘要翻译: 系统被配置为接收包括一组样本的单词; 随机选择样本的一个子集; 从子集中确定具有最低可靠性水平的第一个样本; 选择样品的另一个子集; 从另一个子集中识别具有最低可靠性水平的第二个样本; 并基于所选择的第一样本和所选择的第二样本创建合并的子集。 该系统还被配置为选择样本的另一子集; 从另一个子集中确定具有最低可靠性水平的第三个样本; 从合并的子集中确定与最低可靠性相关联的第四个样本; 基于第四个样本比第三个样本包含在另一个合并子集中更大的概率,创建另一个合并子集; 并根据来自其他合并子集的样本生成另一个单词; 并使用其他单词来处理该单词。

    Forward error correction (FEC) convergence by controlling reliability levels of decoded words in a soft FEC decoder
    3.
    发明授权
    Forward error correction (FEC) convergence by controlling reliability levels of decoded words in a soft FEC decoder 有权
    通过控制软FEC解码器中的解码字的可靠性水平来进行前向纠错(FEC)收敛

    公开(公告)号:US08645788B2

    公开(公告)日:2014-02-04

    申请号:US13341226

    申请日:2011-12-30

    摘要: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

    摘要翻译: 系统接收要进行纠错的第一个字; 识别其中可以反转第一个单词内的编码比特的组合; 基于第一个单词和组合生成候选词; 解码候选词; 确定解码字与第一字之间的距离; 选择与最短距离相关联的解码字之一作为第二个字; 将第二个单词与第一个单词进行比较,以识别第一个单词内的错误; 产生一个值,当误差量小于阈值时,使第一个字的可靠性水平增加; 产生另一个值,当误差量不小于阈值时,使第一个字的可靠性水平降低; 并且基于第一个字,以及该值或另一个值输出第三个字。

    METHOD, SYSTEM, AND APPARATUS FOR INTERPOLATING AN OUTPUT OF AN ANALOG-TO-DIGITAL CONVERTER
    4.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR INTERPOLATING AN OUTPUT OF AN ANALOG-TO-DIGITAL CONVERTER 有权
    用于插入模拟数字转换器输出的方法,系统和装置

    公开(公告)号:US20110291865A1

    公开(公告)日:2011-12-01

    申请号:US12791694

    申请日:2010-06-01

    IPC分类号: H03M7/00

    摘要: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

    摘要翻译: 公开了一种用于对模数转换器(ADC)的输出进行插值的系统,方法和装置,以使得能够以独立于DSP核的采样率的采样速率对ADC进行操作,以便有效地使能操作 以较高的日期率。 根据实施例之一,内插电路耦合在ADC和DSP内核之间,并从ADC接收第一数据速率的第一多个数据采样,并将第二数据的多个样本以第二数据速率提供给 DSP内核; 第二数据速率小于第一数据速率。 根据实施例中的一个,内插电路包括存储器和具有滤波器抽头系数值的FIR滤波器电路,该滤波器抽头系数值被选择以在高频率下提供衰减以减少混叠噪声。

    Adaptive voltage scaling based on the results of forward error correction processing
    5.
    发明授权
    Adaptive voltage scaling based on the results of forward error correction processing 有权
    基于前向纠错处理结果的自适应电压缩放

    公开(公告)号:US09158356B2

    公开(公告)日:2015-10-13

    申请号:US13170747

    申请日:2011-06-28

    摘要: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

    摘要翻译: 在一个实现中,设备可以包括电压调节器电路,数据处理电路和纠错电路,其中纠错电路可以校正由数据处理电路处理的数据中的错误,以获得纠错数据并输出错误 - 已处理数据的已更正版本。 此外,错误监视电路可以输出指示处理数据中的错误级别的错误信号。 控制电路可以接收误差信号并且控制电压调节器电路基于误差信号来调整数据处理电路的电源电压。 在一些实施方案中,控制电路还可以基于其决定,以基于数据处理电路中的可用时序余量来控制电压调节器电路。

    Method, system, and apparatus for interpolating an output of an analog-to-digital converter
    6.
    发明授权
    Method, system, and apparatus for interpolating an output of an analog-to-digital converter 有权
    用于内插模数转换器的输出的方法,系统和装置

    公开(公告)号:US08477056B2

    公开(公告)日:2013-07-02

    申请号:US12791694

    申请日:2010-06-01

    IPC分类号: H03M1/12

    摘要: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

    摘要翻译: 公开了一种用于对模数转换器(ADC)的输出进行插值的系统,方法和装置,以使得能够以独立于DSP核的采样率的采样速率对ADC进行操作,以便有效地使能操作 以较高的日期率。 根据实施例之一,内插电路耦合在ADC和DSP内核之间,并从ADC接收第一数据速率的第一多个数据采样,并将第二数据的多个样本以第二数据速率提供给 DSP内核; 第二数据速率小于第一数据速率。 根据实施例中的一个,内插电路包括存储器和具有滤波器抽头系数值的FIR滤波器电路,该滤波器抽头系数值被选择以在高频率下提供衰减以减少混叠噪声。

    ADAPTIVE VOLTAGE SCALING BASED ON THE RESULTS OF FORWARD ERROR CORRECTION PROCESSING
    7.
    发明申请
    ADAPTIVE VOLTAGE SCALING BASED ON THE RESULTS OF FORWARD ERROR CORRECTION PROCESSING 有权
    基于前向纠错处理结果的自适应电压调整

    公开(公告)号:US20130007516A1

    公开(公告)日:2013-01-03

    申请号:US13170747

    申请日:2011-06-28

    IPC分类号: G06F11/07

    摘要: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

    摘要翻译: 在一个实现中,设备可以包括电压调节器电路,数据处理电路和纠错电路,其中纠错电路可以校正由数据处理电路处理的数据中的错误,以获得纠错数据并输出错误 - 已处理数据的已更正版本。 此外,错误监视电路可以输出指示处理数据中的错误级别的错误信号。 控制电路可以接收误差信号并且控制电压调节器电路基于误差信号来调整数据处理电路的电源电压。 在一些实施方案中,控制电路还可以基于其决定,以基于数据处理电路中的可用时序余量来控制电压调节器电路。

    Coherent detection using coherent decoding and interleaving
    8.
    发明授权
    Coherent detection using coherent decoding and interleaving 有权
    使用相干解码和交织的相干检测

    公开(公告)号:US08861636B2

    公开(公告)日:2014-10-14

    申请号:US13250462

    申请日:2011-09-30

    摘要: A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.

    摘要翻译: 系统被配置为接收与包括对应于与所述信号相关联的有效载荷的数据符号的相位调制信号和控制符号相关联的符号块; 处理控制符号以识别与控制符号相关联的相位噪声量; 基于相位噪声量和参考相位复位与每个数据符号相关联的相位; 将每个数据符号的各个数据样本与其他数据样本进行交织,其中交织的相应数据样本导致与各个数据样本相关联的错误在其它数据样本之间展开,并减少相对于 在交织之前存在的先前数据速率; 并对交错的各个数据样本执行前向纠错。

    PMD-insensitive method of chromatic dispersion estimation for a coherent receiver
    10.
    发明授权
    PMD-insensitive method of chromatic dispersion estimation for a coherent receiver 有权
    相干接收机的色散估计的PMD不敏感方法

    公开(公告)号:US08705986B2

    公开(公告)日:2014-04-22

    申请号:US12926533

    申请日:2010-11-23

    IPC分类号: H04B10/64

    CPC分类号: H04B10/6161 H04B10/6162

    摘要: Consistent with the present disclosure, a method and system for estimating chromatic dispersion of an optical signal in a coherent receiver is provided that is insensitive to polarization mode dispersion (PMD) and other polarization effects in the optical communication system. The effects of chromatic dispersion in the optical system are estimated by first calculating a phase shift between a pair of related frequency domain data outputs of a Fourier transform circuit. The calculated phase shift includes a linear phase component that is proportional to the chromatic dispersion, a DC constant phase component, and a data spectrum component. The calculated phase shift is then averaged over a number of clock cycles to remove the data spectrum components. The time averaged result is used to normalize any effects of PMD from the received signal. A slope of the linear phase component as a function of frequency is then calculated and used to estimate the value for chromatic dispersion. The chromatic dispersion estimate is then used to determine a number of coefficients of an inverse frequency response of the chromatic dispersion in the system, and is used to compensate for the chromatic dispersion.

    摘要翻译: 根据本公开,提供了一种用于估计相干接收机中的光信号的色散的方法和系统,其对于光通信系统中的偏振模色散(PMD)和其它极化效应不敏感。 通过首先计算傅里叶变换电路的一对相关频域数据输出之间的相移来估计光学系统中色散的影响。 所计算的相移包括与色散成比例的直线相位分量,DC恒定相位分量和数据光谱分量。 然后在多个时钟周期内对所计算的相移进行平均以去除数据光谱分量。 时间平均结果用于对接收到的信号的PMD的任何影响进行归一化。 然后计算作为频率的函数的线性相位分量的斜率,并用于估计色散的值。 然后使用色散估计来确定系统中色散的反频率响应的系数数,并且用于补偿色散。