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    Chip decoupling capacitor
    3.
    发明授权
    Chip decoupling capacitor 失效
    芯片去耦电容

    公开(公告)号：US6124625A

    公开(公告)日：2000-09-26

    申请号：US916184

    申请日：1997-08-21

    申请人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    发明人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    IPC分类号： H01L27/02 ,  H01L27/08 ,  H05K1/02 ,  H01L29/00 ,  H01L27/108 ,  H01L29/93

    CPC分类号： H01L27/0805 ,  H01L27/0214 ,  H05K1/0231

    摘要： An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

    摘要翻译： 一个广泛的N沟道晶体管形成的电容网络，其一个节点直接连接到VCC电源总线，另一个节点直接连接VSS电源总线，在整个硅芯片（存储器和逻辑芯片）上可用的所有开放空间中实现， 特别是那些直接在金属电源总线下面的那些，以实现片上电源总线去耦电容器，电容值超过0.001μF。

    Chip decoupling capacitor
    4.
    发明授权
    Chip decoupling capacitor 失效
    芯片去耦电容

    公开(公告)号：US5266821A

    公开(公告)日：1993-11-30

    申请号：US970528

    申请日：1992-11-02

    申请人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    发明人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    IPC分类号： H01L27/02 ,  H01L27/08 ,  H05K1/02

    CPC分类号： H01L27/0214 ,  H01L27/0805 ,  H05K1/0231

    摘要： An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

    摘要翻译： 广泛的N沟道晶体管形成的电容网络，一个节点直接连接到Vcc电源总线，另一个节点直接连接Vss电源总线，在整个硅芯片（存储器和逻辑芯片）上可用的所有开放空间实现， 特别是那些直接在金属电源总线下面的那些，以实现片上电源总线去耦电容器，电容值超过0.001μF。

    Chip decoupling capacitor
    5.
    发明授权
    Chip decoupling capacitor 失效
    芯片去耦电容

    公开(公告)号：US06448628B2

    公开(公告)日：2002-09-10

    申请号：US09492932

    申请日：2000-01-27

    申请人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    发明人： Wen-Foo Chern ,  Ward D. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman

    IPC分类号： H01L2900

    CPC分类号： H01L27/0805 ,  H01L27/0214 ,  H05K1/0231

    摘要： An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

    摘要翻译： 一个广泛的N沟道晶体管形成的电容网络，一个节点直接连接到VCC电源总线，另一个节点直接连接VSS电源总线，在整个硅芯片（存储器以及逻辑芯片）上可用的所有开放空间中实现， 特别是那些直接在金属电源总线下方的器件，以实现片上电源总线去耦电容器，其电容值超过0.001μF。

    Active up-pump for semiconductor sense lines
    6.
    发明授权
    Active up-pump for semiconductor sense lines 失效
    用于半导体感测线的主动上行泵

    公开(公告)号：US4897568A

    公开(公告)日：1990-01-30

    申请号：US252499

    申请日：1988-09-30

    申请人： Wen-Foo Chern ,  Ward D. Parkinson ,  Zhitong Chen ,  Gary M. Johnson ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Wen-Foo Chern ,  Ward D. Parkinson ,  Zhitong Chen ,  Gary M. Johnson ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094 ,  H03K19/017

    CPC分类号： G11C11/4094 ,  H03K19/01742

    摘要： A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.

    摘要翻译： 抽吸电路使用电压检测来将低节点置于VSS + VT的电位，首先将节点接地，然后将节点浮动到VSS + VT电位。 当感测节点处于VSS + VT电位时，感测节点通过泵浦电路的漏电流保持在接地以上的水平。 将数字和数字*线偏置到地面以上的潜在VT可减少电流（安培数）要求，因为数字和数字*线不必完全放电到地面。 感测放大器节点到地的瞬间放电允许感测放大器在初始感测期间像传统的感测放大器一样，从而允许最小的数字/数字*感测电位近似接地加上VT。

    Pull up circuit for digit lines in a semiconductor memory
    7.
    发明授权
    Pull up circuit for digit lines in a semiconductor memory 失效
    上拉电路用于半导体存储器中的数字线

    公开(公告)号：US4924442A

    公开(公告)日：1990-05-08

    申请号：US252494

    申请日：1988-09-30

    申请人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

    摘要翻译： 电压感测电路用于将参考阵列的高电位节点快速上拉至阈值电压（VCC-VT）降低的高电位源的值。 在使能周期期间，高电位节点被预充电到VCC-VT的电位，VCC-VT导通晶体管门控VCC电位。 这将高电位节点尽可能快地拉到高电平，以加速感测过程。 潜在维护电路提供来自高电位源的足够的电流以在高电位节点处保持期望的电位。

    Pull up circuit for sense lines in a semiconductor memory
    8.
    发明授权
    Pull up circuit for sense lines in a semiconductor memory 失效
    上拉电路用于半导体存储器中的感测线

    公开(公告)号：US4914631A

    公开(公告)日：1990-04-03

    申请号：US252585

    申请日：1988-09-30

    申请人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

    摘要翻译： 存储器阵列（例如，DRAM）设置有潜在的维护电路，其提供足够的电流以将存储器阵列的高电位节点保持在预定电位。 在接收到时钟信号并在预定电位门控OFF之后，潜在维护电路被选通。 这允许高压节点被维持，同时减少电流要求。 当与将快速将高节点上拉到VCC-VT（其中VT是晶体管的阈值电压）的电路结合使用时，本发明特别有用。

    Depletion mode chip decoupling capacitor
    9.
    发明授权
    Depletion mode chip decoupling capacitor 失效
    耗尽模式芯片去耦电容

    公开(公告)号：US5032892A

    公开(公告)日：1991-07-16

    申请号：US453861

    申请日：1989-12-20

    申请人： Wen-Foo Chern ,  Ward M. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman ,  James E. O'Toole

    发明人： Wen-Foo Chern ,  Ward M. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman ,  James E. O'Toole

    IPC分类号： H01L27/02 ,  H01L27/08 ,  H05K1/02

    CPC分类号： H01L27/0805 ,  H01L27/0214 ,  H05K1/0231

    摘要： An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.

    摘要翻译： 一个集成的cirucuit配备有耗尽型滤波电容，可以减少电压尖峰，同时避免电容引起的闭锁问题。 耗尽型电容器具有阻挡层，其被掺杂成与集成电路的衬底相反的导电类型，通过掺杂实现，以提供与四价电子相反的差异作为衬底。 阻挡层以避免额外工艺步骤的方式形成为CMOS工艺的一部分。 电容器形成有一个节点连接到接地或基板，另一个节点直接连接到电源总线。 电容器位于整个硅芯片（存储器和逻辑芯片）上的开放空间上，特别是直接在金属电源总线下方，以实现片上电源总线去耦电容器超过0.001μF的电容。

    Reduced latchup in precharging I/O lines to sense amp signal levels
    10.
    发明授权
    Reduced latchup in precharging I/O lines to sense amp signal levels 失效
    在预充电I / O线路中减少闭锁以感测放大器信号电平

    公开(公告)号：US4962326A

    公开(公告)日：1990-10-09

    申请号：US222842

    申请日：1988-07-22

    申请人： Ward D. Parkinson ,  Wen-Foo Chern

    发明人： Ward D. Parkinson ,  Wen-Foo Chern

    IPC分类号： G11C7/10 ,  H03K19/003

    CPC分类号： G11C7/1048 ,  H03K19/00315

    摘要： I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).

    摘要翻译： CMOS电路上的I / O线被预先充电至优选的电压电平，以避免闩锁。 通过使用N沟道晶体管来提供预充电，该预充电的阈值电压（VT）低于偏置电压VCC或（VCC-VT）。 这导致当I / O线浮起后VCC下降时，较低的正向偏置。 通过将预充电电压降低到与阈值电压（VT）相对应的电平，电源电压触发的允许范围增加该量。 这消除了VBE的负凸起的破坏性影响，其将呈现二极管正向偏置条件。 相反，电源可能会碰到（VBE + VT）。