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公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
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3.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS 有权用于制造具有基板接触的集成电路的方法和具有基板接触的集成电路公开(公告)号：US20130256901A1
公开(公告)日：2013-10-03
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
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4.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION 审中-公开用减少电气参数变化制造集成电路的方法公开(公告)号：US20130244388A1
公开(公告)日：2013-09-19
申请号：US13421604
申请日：2012-03-15
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823418 , H01L29/1045 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.
摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。 在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。 在栅堆叠周围形成第二晕环。 然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。
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5.发明授权Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same 有权具有在栅极宽度方向上具有不同厚度的功函数调节层的半导体器件及其制造方法公开(公告)号：US08508001B2
公开(公告)日：2013-08-13
申请号：US13217792
申请日：2011-08-25
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/66772 , H01L29/7834 , H01L29/78654
摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.
摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。
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6.发明申请COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS 有权补充应力衬管改善DGO / AVT器件和聚偏振电阻公开(公告)号：US20120199912A1
公开(公告)日：2012-08-09
申请号：US13023794
申请日：2011-02-09
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。
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7.发明申请Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy 有权晶体管包括嵌入式西格玛形成的顺序形成的半导体合金公开(公告)号：US20120161204A1
公开(公告)日：2012-06-28
申请号：US13232571
申请日：2011-09-14
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
摘要翻译： 在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性 晶体管在其处理期间。 例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。
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8.发明授权Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process 有权制造具有升高的源极/漏极区域的晶体管器件以适应金属硅化物形成过程中的消耗的方法公开(公告)号：US09490344B2
公开(公告)日：2016-11-08
申请号：US13345922
申请日：2012-01-09
IPC分类号： H01L21/02 , H01L21/334 , H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.
摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。
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9.发明授权Methods of forming metal silicide regions on semiconductor devices using different temperatures 有权在使用不同温度的半导体器件上形成金属硅化物区域的方法公开(公告)号：US08815736B2
公开(公告)日：2014-08-26
申请号：US13218089
申请日：2011-08-25
申请人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
发明人： Thilo Scheiper , Peter Javorka , Stefan Flachowsky , Clemens Fitz
IPC分类号： H01L21/8238 , H01L21/44 , H01L21/285
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
摘要翻译： 本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物 每个P掺杂源/漏区中的区域。 该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在 第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。
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10.发明授权Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure 有权在包含高k金属栅电极结构的晶体管中的差分源极/漏极注入间隔物的牺牲间隔法公开(公告)号：US08709902B2
公开(公告)日：2014-04-29
申请号：US13192567
申请日：2011-07-28
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.
摘要翻译： 在复杂的半导体器件中，可以通过使用牺牲隔离元件作为蚀刻掩模而将N沟道晶体管和P沟道晶体管分别完成深漏极和源极区的分布，而不需要任何额外的工艺步骤，并且作为注入掩模 结合用于一种类型晶体管的深漏极和源极区的漏极和源极掺杂物种类。 另一方面，通常的主间隔物可以用于结合另一种晶体管的深漏极和源极区。
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