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1.发明申请Methods and Apparatus for Minimizing Jitter in a Clock Synthesis Circuit that Uses Feedback Interpolation 失效在使用反馈插值的时钟合成电路中最小化抖动的方法和装置公开(公告)号：US20080048734A1
公开(公告)日：2008-02-28
申请号：US11861690
申请日：2007-09-26
IPC分类号： H03B21/00
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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2.发明申请公开(公告)号：US20080260071A1
公开(公告)日：2008-10-23
申请号：US12130732
申请日：2008-05-30
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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3.发明授权Methods and apparatus for generating multiple clocks using feedback interpolation 有权使用反馈插值产生多个时钟的方法和装置公开(公告)号：US07323916B1
公开(公告)日：2008-01-29
申请号：US11321412
申请日：2005-12-29
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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4.发明授权Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation 失效用于最小化使用反馈插值的时钟合成电路中的抖动的方法和装置公开(公告)号：US07436229B2
公开(公告)日：2008-10-14
申请号：US11861690
申请日：2007-09-26
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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5.发明授权公开(公告)号：US08433018B2
公开(公告)日：2013-04-30
申请号：US12130732
申请日：2008-05-30
IPC分类号： H04L7/00
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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6.发明授权公开(公告)号：US07432750B1
公开(公告)日：2008-10-07
申请号：US11296786
申请日：2005-12-07
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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公开(公告)号：US08638896B2
公开(公告)日：2014-01-28
申请号：US12728129
申请日：2010-03-19
申请人： Dean Liu , Marc J. Loinaz , Stefanos Sidiropoulos
发明人： Dean Liu , Marc J. Loinaz , Stefanos Sidiropoulos
IPC分类号： H04L7/00
摘要： A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.
摘要翻译： 用于时钟的电路包括输入数据路径，接收器，一组触发器，至少一个内插器和控制器。 接收器耦合到输入数据路径以接收输入数据。 耦合到接收器的触发器对输入数据进行采样。 耦合到一个或多个触发器的第一内插器接收采样的输入数据。 耦合到第一内插器的控制器通过向第一内插器提供关于输入数据的相位信息来控制第一内插器。 该电路减少了从输入路径传输到输出路径的任何抖动。
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公开(公告)号：US20110228889A1
公开(公告)日：2011-09-22
申请号：US12728129
申请日：2010-03-19
申请人： Dean Liu , Marc J. Loinaz , Stefanos Sidiropoulos
发明人： Dean Liu , Marc J. Loinaz , Stefanos Sidiropoulos
摘要： A circuit for clocking includes an input data path, a receiver, a set of flip-flops, at least one interpolator and a controller. The receiver is coupled to the input data path for receiving input data. The flip-flops, coupled to the receiver, sample the input data. A first interpolator, coupled to one or more of the flip-flops, receives the sampled input data. The controller, coupled to the first interpolator, controls the first interpolator by providing phase information regarding the input data to the first interpolator. The circuit reduces any jitter transferred from the input path to an output path.
摘要翻译： 用于时钟的电路包括输入数据路径，接收器，一组触发器，至少一个内插器和控制器。 接收器耦合到输入数据路径以接收输入数据。 耦合到接收器的触发器对输入数据进行采样。 耦合到一个或多个触发器的第一内插器接收采样的输入数据。 耦合到第一内插器的控制器通过向第一内插器提供关于输入数据的相位信息来控制第一内插器。 该电路减少了从输入路径传输到输出路径的任何抖动。
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9.发明授权Method and apparatus for receive channel data alignment with minimized latency variation 有权用于以最小的延迟变化接收信道数据对准的方法和装置公开(公告)号：US07913104B1
公开(公告)日：2011-03-22
申请号：US11974309
申请日：2007-10-12
申请人： Warren E. Cory , Donald Stark , Dean Liu , Clemenz Portmann
发明人： Warren E. Cory , Donald Stark , Dean Liu , Clemenz Portmann
CPC分类号： H04J3/0685 , G06F1/10 , H04J3/062
摘要： Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.
摘要翻译： 通过利用相同的字节时钟信号，在接收机的整个数据字节处理逻辑中保持千兆位接收器内的数据和时钟同步。 用于对接收到的串行数据流进行反序列化的反序列化时钟信号与物理编码子层（PCS）中使用的分布式字节时钟信号相位相关，从而建立跨物理介质连接（PMA）和PCS层的可靠数据传输 千兆接收机，同时保持已知的固定延迟。 导出的位时钟信号和字节时钟信号之间的相位关系以在每个数据字节内实现粗略数据对齐而不影响等待时间的方式移位。 相反，粗略数据对齐与数据对齐切换过程相结合，以最小化延迟变化来减少数据对齐粒度。
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10.发明授权Method and apparatus for calibrating a delay locked loop charge pump current 有权用于校准延迟锁定环电荷泵电流的方法和装置公开(公告)号：US06788045B2
公开(公告)日：2004-09-07
申请号：US10147594
申请日：2002-05-17
申请人： Claude R. Gauthier , Brian W. Amick , Pradeep Trivedi , Dean Liu
发明人： Claude R. Gauthier , Brian W. Amick , Pradeep Trivedi , Dean Liu
IPC分类号： G01R2312
CPC分类号： H03L7/0812 , H03L7/0896
摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.
摘要翻译： 提供了一种用于后期制造控制延迟锁定环电荷泵电流的校准和调整系统。 校准和调节系统包括改变电荷泵电流量的调节装置。 在延迟锁定环路中对电荷泵电流的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。 可以存储并随后读取电荷泵电流期望的调节量的代表值来调整延迟锁定环路。
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