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    Charge-sharing digital to analog converter and successive approximation analog to digital converter
    1.
    发明授权
    Charge-sharing digital to analog converter and successive approximation analog to digital converter 有权
    电荷共享数模转换器和逐次逼近模数转换器

    公开(公告)号：US07916063B1

    公开(公告)日：2011-03-29

    申请号：US12568172

    申请日：2009-09-28

    申请人： Clemenz Portmann ,  Christoph Lang

    发明人： Clemenz Portmann ,  Christoph Lang

    IPC分类号： H03M1/34

    CPC分类号： H03M1/466

    摘要： In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator.

    摘要翻译： 在一个实施例中，模数转换器包括具有第一输入，第二输入和输出的比较器，第一输入耦合到模拟信号，逐次逼近寄存器，具有耦合到比较器的输出的串行输入， 并且被配置为产生与所述模拟信号相对应的多个控制信号和N位数字值，以及具有耦合到所述多个控制信号的输入的数模转换器，所述数模转换器还包括第一， 第二电容器和第三电容器以及由所述多个控制信号控制的多个开关，并且被配置为将所述第一电容器与所述第二电容器和所述第三电容器相互独立地耦合到所述第二电容器，以在所述第一电容器上共享电荷并充电 在第二电容器上充电的第三电容器上并在第二电容器上产生模拟信号，第二电容器是 耦合到比较器的第二输入端。

    Method and apparatus for receive channel data alignment with minimized latency variation
    2.
    发明授权
    Method and apparatus for receive channel data alignment with minimized latency variation 有权
    用于以最小的延迟变化接收信道数据对准的方法和装置

    公开(公告)号：US07913104B1

    公开(公告)日：2011-03-22

    申请号：US11974309

    申请日：2007-10-12

    申请人： Warren E. Cory ,  Donald Stark ,  Dean Liu ,  Clemenz Portmann

    发明人： Warren E. Cory ,  Donald Stark ,  Dean Liu ,  Clemenz Portmann

    IPC分类号： G06F1/04 ,  G06F1/00 ,  H04L7/00

    CPC分类号： H04J3/0685 ,  G06F1/10 ,  H04J3/062

    摘要： Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

    摘要翻译： 通过利用相同的字节时钟信号，在接收机的整个数据字节处理逻辑中保持千兆位接收器内的数据和时钟同步。 用于对接收到的串行数据流进行反序列化的反序列化时钟信号与物理编码子层（PCS）中使用的分布式字节时钟信号相位相关，从而建立跨物理介质连接（PMA）和PCS层的可靠数据传输 千兆接收机，同时保持已知的固定延迟。 导出的位时钟信号和字节时钟信号之间的相位关系以在每个数据字节内实现粗略数据对齐而不影响等待时间的方式移位。 相反，粗略数据对齐与数据对齐切换过程相结合，以最小化延迟变化来减少数据对齐粒度。

    Method and apparatus for synchronizing a control signal
    6.
    发明授权
    Method and apparatus for synchronizing a control signal 失效
    用于同步控制信号的方法和装置

    公开(公告)号：US06205191B1

    公开(公告)日：2001-03-20

    申请号：US08897658

    申请日：1997-07-21

    申请人： Clemenz Portmann ,  John B. Dillon

    发明人： Clemenz Portmann ,  John B. Dillon

    IPC分类号： H04L700

    CPC分类号： H04L7/02 ,  G06F1/10 ,  H04L7/0045

    摘要： A synchronization circuit for gradually shifting the phase domain of a control signal to permit synchronization of a signal with a clock signal in a different phase domain in a system with a single frequency, but arbitrary phase relationship. The present invention allows a control signal in the phase domain of an internal clock to be synchronized with an external clock, when the phase domain of the external clock differs substantially from that of the internal clock. In synchronizing the control signal to the external clock, the present invention avoids the generation of runt pulses while providing a control signal synchronized to the external clock in the least amount of time feasible (i.e., with the lowest latency time). Because the present invention has no failure modes due to timing relationships, MTBF is infinite for failures caused by such relationships and therefore need not be a concern. This also implies that no risk is posed to the proper operation of the circuits driven thereby.

    摘要翻译： 一种同步电路，用于逐渐移动控制信号的相位域，以允许在具有单个频率但是任意的相位关系的系统中，使信号与不同相位域中的时钟信号同步。 当外部时钟的相位域与内部时钟的相位域显着不同时，本发明允许内部时钟的相位域中的控制信号与外部时钟同步。 在使控制信号与外部时钟同步时，本发明避免了在可能的最短时间内（即以最低的等待时间）提供与外部时钟同步的控制信号的同时产生欠压脉冲。 由于本发明由于定时关系而没有故障模式，因此对于由这种关系引起的故障，MTBF是无限的，因此不需要担心。 这也意味着对由此驱动的电路的正常操作没有风险。