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    Transistor with embedded Si/Ge material having reduced offset to the channel region
    1.
    发明授权
    Transistor with embedded Si/Ge material having reduced offset to the channel region 有权
    具有嵌入的Si / Ge材料的晶体管具有减小到沟道区的偏移

    公开(公告)号：US08071442B2

    公开(公告)日：2011-12-06

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

    Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter
    4.
    发明授权
    Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter 有权
    工艺流程可以减少P-活性区域中的空穴缺陷并减少跨晶圆阈值电压的散射

    公开(公告)号：US08703551B2

    公开(公告)日：2014-04-22

    申请号：US13102680

    申请日：2011-05-06

    申请人： Stephan Kronholz ,  Andreas Ott

    发明人： Stephan Kronholz ,  Andreas Ott

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L21/302

    CPC分类号： H01L21/30608 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行至少一个蚀刻工艺以减小半导体衬底的P活性区域的厚度，从而限定凹陷的P活性区域，在处理室中执行选择性地形成 在凹陷的P活性区域上形成半导体材料的沉积层，其中执行所述至少一个蚀刻工艺的步骤在所述处理室的外部进行，并且在所述处理室中进行蚀刻处理以减小所述至少一个蚀刻工艺的厚度， 半导体材料的沉积层。

    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION
    7.
    发明申请
    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION 有权
    具有嵌入式SI / GE材料的晶体管具有减少偏移到通道区域

    公开(公告)号：US20100078689A1

    公开(公告)日：2010-04-01

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

    Process Flow to Reduce Hole Defects in P-Active Regions and to Reduce Across-Wafer Threshold Voltage Scatter
    8.
    发明申请
    Process Flow to Reduce Hole Defects in P-Active Regions and to Reduce Across-Wafer Threshold Voltage Scatter 有权
    工艺流程减少P-活性区域中的孔缺陷并减少跨晶片阈值电压分散

    公开(公告)号：US20120282763A1

    公开(公告)日：2012-11-08

    申请号：US13102680

    申请日：2011-05-06

    申请人： Stephan Kronholz ,  Andreas Ott

    发明人： Stephan Kronholz ,  Andreas Ott

    IPC分类号： H01L21/306

    CPC分类号： H01L21/30608 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行至少一个蚀刻工艺以减小半导体衬底的P活性区域的厚度，从而限定凹陷的P活性区域，在处理室中执行选择性地形成 在凹陷的P活性区域上形成半导体材料的沉积层，其中执行所述至少一个蚀刻工艺的步骤在所述处理室的外部进行，并且在所述处理室中进行蚀刻处理以减小所述至少一个蚀刻工艺的厚度， 半导体材料的沉积层。