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    ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION
    2.
    发明申请
    ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A RECESS PRIOR TO THE WELL IMPLANTATION 有权
    通过在较好的植入前形成一个通道，提高通道半导体合金的沉积均匀性

    公开(公告)号：US20110156172A1

    公开(公告)日：2011-06-30

    申请号：US12908053

    申请日：2010-10-20

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

    摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

    摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
    4.
    发明授权
    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices 有权
    在密集封装的半导体器件中，在沟槽隔离结构中埋设蚀刻停止层以获得出色的表面平面度

    公开(公告)号：US08334573B2

    公开(公告)日：2012-12-18

    申请号：US12858727

    申请日：2010-08-18

    申请人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    发明人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    IPC分类号： H01L27/088

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

    摘要翻译： 先进的半导体器件中的沟槽隔离结构的材料侵蚀可以通过在早期制造阶段中合并适当的掩模层堆叠来减少。 例如，氮化硅材料可以在用于图案化有源区域并在其中形成应变诱导半导体合金的序列之前作为掩埋蚀刻停止层引入，其中特别地，在选择性外延生长工艺之前的相应的清洁工艺 已经被确定为在沉积层间介电材料时引起沉积相关不规则的主要来源。

    Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures
    6.
    发明申请
    Test Structure for Controlling the Incorporation of Semiconductor Alloys in Transistors Comprising High-K Metal Gate Electrode Structures 有权
    用于控制包含高K金属栅电极结构的晶体管中半导体合金的引入的测试结构

    公开(公告)号：US20120001174A1

    公开(公告)日：2012-01-05

    申请号：US12965341

    申请日：2010-12-10

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    IPC分类号： H01L23/544 ,  H01L21/66

    CPC分类号： H01L22/12 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.

    摘要翻译： 当在复杂的半导体器件中形成临界阈值调节半导体合金和/或应变诱导嵌入式半导体材料时，可以通过提供适当设计的测试结构，基于机械收集的轮廓测量数据来有效地监测至少相应的蚀刻工艺。 因此，可以通过机械获得的轮廓测量数据有效地监视和/或控制在体半导体器件上执行的复杂工艺序列而没有显着的延迟。 例如，可以实现在用于非SOI器件的复杂高k金属栅极电极结构中提供阈值调节半导体合金时的均匀性。

    TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE
    7.
    发明申请
    TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE 有权
    包含嵌入式半导体合金的晶体管在栅极电极延伸的漏极和源极区域

    公开(公告)号：US20100219474A1

    公开(公告)日：2010-09-02

    申请号：US12709966

    申请日：2010-02-22

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78654

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

    摘要翻译： 应变诱导半导体合金可以基于可以深深延伸到栅电极结构下方的空穴形成，这可以通过使用两个蚀刻工艺的顺序来实现。 在第一蚀刻工艺中，可以基于良好限定的横向偏移来形成空腔，以确保栅电极结构的完整性，并且在随后的蚀刻工艺中，空腔可以在横向方向上增加，同时可靠地保持 通道区域的一部分。 因此，可以通过将应变诱导材料适当地定位在通道区域正下方而不损害栅电极结构的完整性来增加应变诱导效率。

    Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography
    8.
    发明授权
    Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography 有权
    半导体器件包括形成有减少的STI形貌的沟道半导体合金

    公开(公告)号：US08748275B2

    公开(公告)日：2014-06-10

    申请号：US13191993

    申请日：2011-07-27

    申请人： Hans-Juergen Thees ,  Stephan Kronholz ,  Maciej Wiatr

    发明人： Hans-Juergen Thees ,  Stephan Kronholz ,  Maciej Wiatr

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823807 ,  H01L21/76232 ,  H01L21/823878

    摘要： In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.

    摘要翻译： 在复杂的半导体器件中，半导体合金，例如硅/锗形式的阈值调节半导体材料，可以在早期制造阶段中选择性地在某些活性区域中提供，其中明显的凹陷程度和材料损失 在隔离区域中，可以通过在隔离区域上选择性地提供保护材料层来避免。 例如，在一些说明性实施例中，硅材料可以选择性地沉积在隔离区域上。

    Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures
    9.
    发明授权
    Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures 有权
    用于控制在包括高k金属栅电极结构的晶体管中引入半导体合金的测试结构

    公开(公告)号：US08673668B2

    公开(公告)日：2014-03-18

    申请号：US12965341

    申请日：2010-12-10

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Rainer Giedigkeit

    IPC分类号： H01L21/00

    CPC分类号： H01L22/12 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.

    摘要翻译： 当在复杂的半导体器件中形成临界阈值调节半导体合金和/或应变诱导嵌入式半导体材料时，可以通过提供适当设计的测试结构，基于机械收集的轮廓测量数据来有效地监测至少相应的蚀刻工艺。 因此，可以通过机械获得的轮廓测量数据有效地监视和/或控制在体半导体器件上执行的复杂工艺序列而没有显着的延迟。 例如，可以实现在用于非SOI器件的复杂高k金属栅极电极结构中提供阈值调节半导体合金时的均匀性。

    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode
    10.
    发明授权
    Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode 有权
    晶体管包括在栅极电极下方延伸的漏极和源极区域中的嵌入式半导体合金

    公开(公告)号：US08460980B2

    公开(公告)日：2013-06-11

    申请号：US12709966

    申请日：2010-02-22

    申请人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    发明人： Stephan Kronholz ,  Maciej Wiatr ,  Matthias Kessler

    IPC分类号： H01L27/12 ,  H01L27/762

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78654

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

    摘要翻译： 应变诱导半导体合金可以基于可以深深延伸到栅电极结构下方的空穴形成，这可以通过使用两个蚀刻工艺的顺序来实现。 在第一蚀刻工艺中，可以基于良好限定的横向偏移来形成空腔，以确保栅电极结构的完整性，并且在随后的蚀刻工艺中，空腔可以在横向方向上增加，同时可靠地保持 通道区域的一部分。 因此，可以通过将应变诱导材料适当地定位在通道区域正下方而不损害栅电极结构的完整性来增加应变诱导效率。