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    HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION
    5.
    发明申请
    HORIZONTAL EPITAXY FURNACE FOR CHANNEL SIGE FORMATION 有权
    水平信号形成的水平外露炉

    公开(公告)号：US20130302973A1

    公开(公告)日：2013-11-14

    申请号：US13466234

    申请日：2012-05-08

    申请人： Joanna Wasyluk ,  Yew Tuck Chow ,  Stephan Kronholz ,  Lindarti Purwaningsih ,  Ines Becker

    发明人： Joanna Wasyluk ,  Yew Tuck Chow ,  Stephan Kronholz ,  Lindarti Purwaningsih ,  Ines Becker

    IPC分类号： H01L21/205 ,  H01L21/306

    CPC分类号： H01L21/823807 ,  C23C16/45578 ,  C23C16/4587 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823878

    摘要： A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

    摘要翻译： 提供一种方法和装置，用于在水平取向的处理炉内的凹陷区域内凹陷PFET的沟道区和外延生长沟道SiGe。 实施例包括在晶片的前侧形成n沟道区域和p沟道区域以及至少一个附加晶片，n沟道区域和p沟道区域分别对应于用于形成NFET和PFET的位置; 将晶片放置在具有顶表面和底表面的水平取向的炉中，其中晶片在顶表面和底表面之间垂直取向; 使炉内的晶片的p沟道区域凹陷; 并且在炉内凹陷的p沟道区中外延生长cSiGe，而没有孔缺陷。

    Methods for PFET fabrication using APM solutions
    6.
    发明授权
    Methods for PFET fabrication using APM solutions 有权
    使用APM解决方案的PFET制造方法

    公开(公告)号：US08703620B2

    公开(公告)日：2014-04-22

    申请号：US13564071

    申请日：2012-08-01

    申请人： Joanna Wasyluk ,  Stephan Kronholz ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

    发明人： Joanna Wasyluk ,  Stephan Kronholz ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02057 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878

    摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

    摘要翻译： 一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。 第一部分和第二部分通过浅沟槽隔离特征电隔离。 该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。 提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。 该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

    EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES
    7.
    发明申请
    EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES 有权
    外来通道形成方法和结构

    公开(公告)号：US20130210216A1

    公开(公告)日：2013-08-15

    申请号：US13369856

    申请日：2012-02-09

    申请人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    发明人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66651 ,  H01L21/02035 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7833

    摘要： A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

    摘要翻译： 在每个批处理反应器的多个晶片中形成场效应晶体管（FET）的方法包括：在其中提供具有至少一个具有基本上平坦的外表面的至少一个半导体（SC）区域的衬底，修改该基本平坦的外表面以形成凸 在曲面上形成外延半导体层，并且在形成在基板上的场效应晶体管中并入外延层。 当SC区域是硅时，外延层可以包括硅 - 锗。 在优选实施例中，外延层形成FET通道的一部分。 由于凸向外弯曲的表面，即使在每批容纳多达100个或更多个基底的高体积反应器中形成时，其上生长的外延层也具有更均匀的厚度。 获得具有更均匀性能的FET，从而大大提高制造成品率并降低成本。

    Epitaxial channel formation methods and structures
    8.
    发明授权
    Epitaxial channel formation methods and structures 有权
    外延通道形成方法和结构

    公开(公告)号：US09548378B2

    公开(公告)日：2017-01-17

    申请号：US13369856

    申请日：2012-02-09

    申请人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    发明人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

    CPC分类号： H01L29/66651 ,  H01L21/02035 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7833

    摘要： A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

    摘要翻译： 在每个批处理反应器的多个晶片中形成场效应晶体管（FET）的方法包括：在其中提供具有至少一个具有基本上平坦的外表面的至少一个半导体（SC）区域的衬底，修改该基本平坦的外表面以形成凸 在曲面上形成外延半导体层，并且在形成在基板上的场效应晶体管中并入外延层。 当SC区域是硅时，外延层可以包括硅 - 锗。 在优选实施例中，外延层形成FET通道的一部分。 由于凸向外弯曲的表面，即使在每批容纳多达100个或更多个基底的高体积反应器中形成时，其上生长的外延层也具有更均匀的厚度。 获得具有更均匀性能的FET，从而大大提高制造成品率并降低成本。

    Enhancing selectivity during formation of a channel semiconductor alloy by a wet oxidation process
    9.
    发明授权
    Enhancing selectivity during formation of a channel semiconductor alloy by a wet oxidation process 有权
    通过湿式氧化工艺在沟道半导体合金形成过程中提高选择性

    公开(公告)号：US08283225B2

    公开(公告)日：2012-10-09

    申请号：US12824614

    申请日：2010-06-28

    申请人： Stephan Kronholz ,  Carsten Reichel ,  Falk Graetshe ,  Boris Bayha

    发明人： Stephan Kronholz ,  Carsten Reichel ,  Falk Graetshe ,  Boris Bayha

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823462

    摘要： High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy.

    摘要翻译： 基于在一种类型的晶体管的沟道区域中形成的阈值调节半导体合金形成高k金属栅电极结构，其可以基于使用氧化物硬掩模生长掩模的选择性外延生长技术来实现。 在湿式氧化工艺的基础上，硬掩模可以具有优异的厚度均匀性。 因此，这可以允许在选择性外延生长工艺之前的再工作衬底，例如考虑到排队时间违规，同时还在不需要阈值调节半导体合金的晶体管中提供优异的晶体管特性。