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1.发明申请METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES 失效用于比较光刻处理条件和或数据准备过程的方法和系统公开(公告)号：US20120107969A1
公开(公告)日：2012-05-03
申请号：US12914212
申请日：2010-10-28
CPC分类号： G03F7/705
摘要： A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.
摘要翻译： 在为一组数据准备参数和光刻处理条件生成的模拟光刻图案中识别一组光学规则检查器（ORC）标记。 每个ORC标记识别模拟光刻图案中违反ORC规则的特征。 在每个ORC标记中定义一个中心线，并且在每个中心线周围生成最小尺寸区域，其最小宽度符合ORC的规则。 通过从最小尺寸区域去除与ORC标记重叠的区域，在每个ORC标记周围定义故障区域。 添加所有故障区域的区域以定义模拟光刻图案的特征。 可以通过修改数据准备参数和光刻处理条件的集合来评估多个模拟光刻图案或迭代降低的缺点。
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2.发明授权Method and system for comparing lithographic processing conditions and or data preparation processes 失效比较光刻处理条件和/或数据准备过程的方法和系统公开(公告)号：US08381141B2
公开(公告)日：2013-02-19
申请号：US12914212
申请日：2010-10-28
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.
摘要翻译： 在为一组数据准备参数和光刻处理条件生成的模拟光刻图案中识别一组光学规则检查器（ORC）标记。 每个ORC标记识别模拟光刻图案中违反ORC规则的特征。 在每个ORC标记中定义一个中心线，并且在每个中心线周围生成最小尺寸区域，其最小宽度符合ORC的规则。 通过从最小尺寸区域去除与ORC标记重叠的区域，在每个ORC标记周围定义故障区域。 添加所有故障区域的区域以定义模拟光刻图案的特征。 可以通过修改数据准备参数和光刻处理条件的集合来评估多个模拟光刻图案或迭代降低的缺点。
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3.发明授权Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs 失效用于执行蒙特卡罗模拟以预测集成电路设计中的覆盖故障的方法公开(公告)号：US06892365B2
公开(公告)日：2005-05-10
申请号：US10249524
申请日：2003-04-16
申请人： James A. Culp , Mark A. Lavin , Robert T. Sayah
发明人： James A. Culp , Mark A. Lavin , Robert T. Sayah
IPC分类号： H01L21/027 , G06F17/50
CPC分类号： G06F17/5081
摘要： A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.
摘要翻译： 预测半导体晶片的相邻的，光刻制造的层上的电路配置的覆盖失效的方法包括提供在半导体晶片的一个或多个相邻层上光刻制造的电路部分的设计配置，然后预测每个电路的形状和对准 每个相邻层上的部分使用用于过程波动或未对准误差的一个或多个预定值。 然后，该方法确定预测形状和电路部分的对准的重叠的尺寸，并将确定的重叠尺寸与理论最小值进行比较，以确定重叠的预测尺寸是否失败。 使用不同的过程波动值和未对准误差值，然后对提供的设计配置迭代重复这些步骤，以确定重叠的预测维度是否失败，并报告故障的测量。
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4.发明授权Method for selecting hierarchical interactions in a hierarchical shapes processor 失效在分层形状处理器中选择分层交互的方法公开(公告)号：US06243854B1
公开(公告)日：2001-06-05
申请号：US09067832
申请日：1998-04-28
IPC分类号： G06F1710
CPC分类号： G06T11/60
摘要： The method for selecting hierarchical interaction in a hierarchical shapes processor increases the operator's access and control over the handling of the design's hierarchical structure. The shapes of each cell are considered in accordance with a specified hierarchical relationship having constraints defined by the chosen mode of shape processing. The hierarchical relationships provide additional shape processing modes depending on the operator's physical design requirements.
摘要翻译： 用于在分层形状处理器中选择分层交互的方法增加了操作者对设计层级结构的处理的访问和控制。 每个单元的形状根据具有由所选择的形状处理模式限定的约束的指定分层关系来考虑。 分层关系根据操作员的物理设计要求提供额外的形状处理模式。
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公开(公告)号：US07823094B2
公开(公告)日：2010-10-26
申请号：US11621383
申请日：2007-01-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/504 , G06F2217/12 , Y02P90/265
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.
摘要翻译： 一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。 提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的串行化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。 模式搜索可以包括例如预定义模式搜索和冗余模式搜索。
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公开(公告)号：US08423947B2
公开(公告)日：2013-04-16
申请号：US12047566
申请日：2008-03-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.
摘要翻译： 一种格栅字形几何对象（L3GO）集成电路（IC）设计的方法，其中L3GO电路设计中的至少一个级间连接在L3GO网格上表示为点阵字形（PMG）。 每个PMG在下一个相邻（上和下）层上连接一对导体，并包括一个包含在笼中的点字形的阵列（一维或二维）。 点字形可以具有均匀的尺寸并且可以在最小间距上。 每个PMG还可以包括在上下层的凸缘。 默认法兰确保足够的覆盖由点字形表示的切割形状。
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公开(公告)号：US20090235215A1
公开(公告)日：2009-09-17
申请号：US12047566
申请日：2008-03-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.
摘要翻译： 一种格栅字形几何对象（L3GO）集成电路（IC）设计的方法，其中L3GO电路设计中的至少一个级间连接在L3GO网格上表示为点阵字形（PMG）。 每个PMG在下一个相邻（上和下）层上连接一对导体，并包括一个包含在笼中的点字形的阵列（一维或二维）。 点字形可以具有均匀的尺寸并且可以在最小间距上。 每个PMG还可以包括在上下层的凸缘。 默认法兰确保足够的覆盖由点字形表示的切割形状。
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公开(公告)号：US6055367A
公开(公告)日：2000-04-25
申请号：US250909
申请日：1999-02-16
CPC分类号： H01L27/0207 , G06F17/5068
摘要： A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.
摘要翻译： 提供了一种基于现有VLSI CAD数据库电路设计自动生成补偿半导体器件的方法。 优选的方法形成多个边缘投影形状，其与有源区域形状相交以形成门边缘形状。 门边缘形状和边缘形状的残差根据其相对位置进行分类。 然后根据它们的相对位置选择性地偏置这些形状，然后用于补偿现有的栅极导体形状。 因此，该方法提供了一种基于现有栅极，扩散和植入物设计为n沟道和p沟道器件生成具有补偿栅极长度的栅极结构的方法。 该系统具有产生设计的优点，其细节关注对光刻性能产生不利影响的慢跑的放置和最小化。
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公开(公告)号：US20080165192A1
公开(公告)日：2008-07-10
申请号：US11621383
申请日：2007-01-09
IPC分类号： G06T11/00
CPC分类号： G06F17/5068 , G06F17/504 , G06F2217/12 , Y02P90/265
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.
摘要翻译： 一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。 提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的序列化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。 模式搜索可以包括例如预定义模式搜索和冗余模式搜索。
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公开(公告)号：US07814443B2
公开(公告)日：2010-10-12
申请号：US11623541
申请日：2007-01-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout; and a graph-based pattern matching system that can identify potential matches amongst variable patterns in the glyph layout.
摘要翻译： 一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。 提供一种系统，其包括用于使用模式描述语言定义可变模式以创建字形布局的系统; 以及可以识别字形布局中的可变图案之间的潜在匹配的基于图形的模式匹配系统。
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