公开(公告)号：US06445610B1

公开(公告)日：2002-09-03

申请号：US09929611

申请日：2001-08-14

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

摘要翻译： 在包含许多存储单元的数字线和读出放大器之间的DRAM器件中的隔离晶体管的栅极提供可变电压。 隔离晶体管的栅极被提供为在读取时间期间高于电源电压的电压，以确保数字线上的小差分电压被正确读取。 在感测时间提供较低的电压，使得隔离门在感测时间期间提供更高的电阻。 在恢复时间期间，隔离栅极电压再次升高到高于工作电压，以最小化隔离晶体管阈值电压Vt的影响。在另外的实施例中，仅在恢复时间期间提供较高电压，并且读取和检测电压在 更高和更低的电压。

公开(公告)号：US06219293B1

公开(公告)日：2001-04-17

申请号：US09388126

申请日：1999-09-01

申请人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

发明人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C11/4074

摘要： An internal voltage regulator for a synchronous random access memory “SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

摘要翻译： 用于同步随机存取存储器“SDRAM”的内部电压调节器）使用调节器电路来向不同于向SDRAM的阵列供电的调节器电路的电荷泵供电。 调节器为电荷泵提供输出电压，当外部电源电压提高到正常工作范围以上时，电荷泵保持恒定。 相比之下，向阵列供电的稳压电路随着电源电压增加超过正常工作范围而增加。 因此，电压调节器允许阵列以相对较高的调节输出电压进行压力测试，而不会对电荷泵施加过多的，潜在的破坏性的稳压输出电压。

公开(公告)号：US5274276A

公开(公告)日：1993-12-28

申请号：US904814

申请日：1992-06-26

申请人： Stephen L. Casper ,  Stephen R. Porter

发明人： Stephen L. Casper ,  Stephen R. Porter

IPC分类号： H03K17/06 ,  H03K19/003 ,  H03K17/08

CPC分类号： H03K17/063 ,  H03K19/00384

摘要： The invention is an output driver circuit of a dynamic random access memory (DRAM) wherein the output driver is wired in a push-pull configuration. The push-pull configuration comprises a pull-up portion and a pull-down portion serially connected at an output node. The pull-up portion comprises a an n-channel metal oxide semiconductor (NMOS) transistor having a gate potential determined by a programmable circuit. In the preferred embodiment the programmable circuit provides a potential to the gate node of the NMOS that is directly proportional to the supply potential until a maximum programmed gate potential is reached. The programmable circuit maintains the maximum programmed gate potential for further increases in the supply potential. The pull-down portion comprises a pull-down NMOS transistor interposed between the output node and ground. The pull-down NMOS transistor is controlled by a pull-down signal on the gate node. When actuated the pull-down transistor provides a low logic level at the output node. The invention is also the method of driving a potential to the output node.

摘要翻译： 本发明是动态随机存取存储器（DRAM）的输出驱动器电路，其中输出驱动器以推挽配置被布线。 推挽配置包括在输出节点处串联连接的上拉部分和下拉部分。 上拉部分包括具有由可编程电路确定的栅极电位的n沟道金属氧化物半导体（NMOS）晶体管。 在优选实施例中，可编程电路向NMOS的栅极节点提供与供电电位成正比的电位，直到达到最大编程的栅极电位。 可编程电路保持最大编程门电位，以进一步提高电源电位。 下拉部分包括插入在输出节点和地之间的下拉式NMOS晶体管。 下拉式NMOS晶体管由栅极节点上的下拉信号控制。 当启动时，下拉晶体管在输出节点提供低逻辑电平。 本发明也是将电位驱动到输出节点的方法。

公开(公告)号：US06385098B2

公开(公告)日：2002-05-07

申请号：US09836947

申请日：2001-04-17

申请人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

发明人： Hal W. Butler ,  Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C1604

CPC分类号： G11C11/4074

摘要： An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

摘要翻译： 用于同步随机存取存储器（“SDRAM”）的内部电压调节器使用调节器电路来为与将SDRAM供电的稳压器电路分离的电荷泵供电。 调节器为电荷泵提供输出电压，当外部电源电压提高到正常工作范围以上时，电荷泵保持恒定。 相比之下，向阵列供电的稳压电路随着电源电压增加超过正常工作范围而增加。 因此，电压调节器允许阵列以相对较高的调节输出电压进行压力测试，而不会对电荷泵施加过多的，潜在的破坏性的稳压输出电压。

公开(公告)号：US5369317A

公开(公告)日：1994-11-29

申请号：US989252

申请日：1992-12-11

申请人： Stephen L. Casper ,  Stephen R. Porter

发明人： Stephen L. Casper ,  Stephen R. Porter

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C11/419 ,  H03K19/003 ,  H03K17/08

CPC分类号： H03K19/00315 ,  G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  H03K19/00384

摘要： The invention is a circuit and method for controlling a high potential at a significant node by controlling the potential at a control input to an electrical device in electrical communication with the significant node. The potential of the control input is controlled by a control circuit. In a first embodiment the control circuit is a potential generator, and in a second embodiment the control circuit is a programmable circuit. The programmable circuit provides a potential at the control input that is directly proportional to a supply potential until a maximum potential is reached at which time the control input is maintained at the maximum potential.

摘要翻译： 本发明是一种用于通过控制与重要节点电通信的电气设备的控制输入处的电位来控制重要节点处的高电位的电路和方法。 控制输入​​的电位由控制电路控制。 在第一实施例中，控制电路是电位发生器，在第二实施例中，控制电路是可编程电路。 可编程电路在控制输入端提供与供电电位成正比的电位，直到达到最大电位，此时控制输入保持在最大电位。

公开(公告)号：US06275409B1

公开(公告)日：2001-08-14

申请号：US09293027

申请日：1999-04-16

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C1124

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

摘要翻译： 在包含许多存储单元的数字线和读出放大器之间的DRAM器件中的隔离晶体管的栅极提供可变电压。 隔离晶体管的栅极被提供为在读取时间期间高于电源电压的电压，以确保数字线上的小差分电压被正确读取。 在感测时间提供较低的电压，使得隔离门在感测时间期间提供更高的电阻。 在恢复时间期间，隔离栅极电压再次升高到高于工作电压，以最小化隔离晶体管阈值电压Vt的影响。在另外的实施例中，仅在恢复时间期间提供较高电压，并且读取和检测电压在 更高和更低的电压。

公开(公告)号：US5901078A

公开(公告)日：1999-05-04

申请号：US878657

申请日：1997-06-19

申请人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

发明人： Stephen R. Porter ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/24

CPC分类号： G11C7/06 ,  G11C11/4091

摘要： A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

公开(公告)号：US07245548B2

公开(公告)日：2007-07-17

申请号：US10900246

申请日：2004-07-27

申请人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

发明人： Scott J. Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay S. Dixit ,  Scot M. Graham ,  Stephen R. Porter ,  Ethan A. Williford

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C11/4085

摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

公开(公告)号：US06438049B1

公开(公告)日：2002-08-20

申请号：US09256125

申请日：1999-02-24

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

摘要： A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.

摘要翻译： 描述了用于快速平衡动态随机存取存储器件的存储器阵列的成对数字行的方法和电路。 平衡电路包括耦合到读出放大器电路的偏置电路，用于在测试期间调节平衡电压。 描述了通过调整平衡电压直到检测到错误来测试存储单元余量的方法。 偏置电路被描述为耦合到交叉耦合n型放大器的共模的上拉晶体管。

公开(公告)号：US06396300B1

公开(公告)日：2002-05-28

申请号：US09467667

申请日：1999-12-17

申请人： Daniel R. Loughmiller ,  Stephen R. Porter

发明人： Daniel R. Loughmiller ,  Stephen R. Porter

IPC分类号： H03K1900

CPC分类号： H03K19/1732 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H03K19/1731

摘要： A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.