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1.发明授权Methods of using one of a plurality of configuration bitstreams for an integrated circuit 有权使用多个配置比特流中的一个用于集成电路的方法公开(公告)号：US07853916B1
公开(公告)日：2010-12-14
申请号：US11974355
申请日：2007-10-11
IPC分类号： G06F17/50 , H03K19/00 , H03K17/693
CPC分类号： H03K17/693
摘要： Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g., collision penalties) derived from at least two of the plurality of implementations; determining a cost for each implementation based upon the cost function; optimizing an implementation of the design by minimizing the cost of the implementation; generating a plurality of configuration bitstreams for the plurality of implementations; and outputting the plurality of configuration bitstreams.
摘要翻译： 公开了在集成电路中使用多个配置比特流中的一个的方法。 一种示例性方法包括分析设计的多个实现以确定实现中的定时的初始变化; 修改实现以减少实现中的时序变化; 以及输出多个配置比特流，用于具有相对于初始定时变化而减小的定时变化的实现。 另一种方法包括为设计生成多个实现; 基于从所述多个实现中的至少两个导出的成本（例如，冲突惩罚），为所述设计生成成本函数; 根据成本函数确定每个实现的成本; 通过最小化实施成本来优化设计的实施; 为所述多个实现产生多个配置比特流; 并输出多个配置比特流。
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公开(公告)号：US08872536B1
公开(公告)日：2014-10-28
申请号：US13069319
申请日：2011-03-22
IPC分类号： G01R31/02
CPC分类号： G01R31/2894 , H01L22/14 , H01L22/20
摘要： An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.
摘要翻译： 公开了一种用于表征模具的方法的实施例。 该方法的实施例包括测量模具的质量度量，以及在最终测试阶段之前确定模具的质量度量是否满足第一约束，其中第一约束比最终的第二约束更严格 测试阶段为模具的质量度量。
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3.发明授权公开(公告)号：US08966253B1
公开(公告)日：2015-02-24
申请号：US12791668
申请日：2010-06-01
CPC分类号： H04L63/123 , G06F9/30145 , G06F21/572 , G06F21/76
摘要： A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentication code (MAC). At least a portion of the instructions is initially stored in a memory of the programmable device without programming the configuration registers. At least one actual MAC is computed based on the bitstream using a hash algorithm. The at least one actual MAC is compared with the at least one embedded MAC, respectively. Each instruction stored in the memory is executed to program the configuration registers until any one of the at least one actual MAC is not the same as a corresponding one of the at least one embedded MAC, after which any remaining instructions in the memory are not executed.
摘要翻译： 描述用于认证用于配置可编程设备的比特流的方法和装置。 在一个示例中，经由可编程设备的配置端口接收比特流，比特流包括用于编程可编程设备的配置寄存器和至少一个嵌入式消息认证码（MAC）的指令。 指令的至少一部分最初被存储在可编程设备的存储器中，而不对配置寄存器进行编程。 使用散列算法基于比特流计算至少一个实际的MAC。 将至少一个实际的MAC分别与至少一个嵌入式MAC进行比较。 执行存储在存储器中的每个指令以对配置寄存器进行编程，直到至少一个实际MAC中的任何一个与至少一个嵌入式MAC中的对应的一个不相同，之后不执行存储器中的任何剩余指令 。
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4.发明授权Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit 有权可编程集成电路和一种能够检测篡改提供给可编程集成电路的数据的方法公开(公告)号：US08909941B1
公开(公告)日：2014-12-09
申请号：US13077814
申请日：2011-03-31
IPC分类号： G06F21/00
CPC分类号： H04L63/1466 , G06F21/64 , G06F21/76
摘要： A method of enabling detection of tampering with data provided to a programmable integrated circuit is described. The method comprises modifying a portion of the data to establish randomness in the data; and inserting, by a computer, a redundancy check value in the portion, wherein the redundancy check value is based upon the modified portion of the data. A programmable integrated circuit is also described.
摘要翻译： 描述了能够检测到提供给可编程集成电路的数据的篡改的方法。 该方法包括修改数据的一部分以在数据中建立随机性; 并且由计算机插入所述部分中的冗余校验值，其中所述冗余校验值基于所述数据的修改部分。 还描述了可编程集成电路。
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公开(公告)号：US08416950B1
公开(公告)日：2013-04-09
申请号：US13082271
申请日：2011-04-07
IPC分类号： H04L29/06
CPC分类号： H04L9/0866
摘要： An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fingerprint, an encrypted data in order to extract data. In one embodiment, the propagation delay of various circuit elements are used to generate the fingerprint. In another embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In yet another embodiment, a ratio of measurable values is used to generate the fingerprint. In another embodiment, differences in transistor threshold voltages are used to generate the fingerprint. In yet another embodiment, variations in line widths are used to generate the fingerprint.
摘要翻译： 集成电路包括指纹元件和解密电路。 指纹元件产生指纹，其中指纹是可重现的，并且表示集成电路设备独有的固有制造工艺特性。 解密电路使用基于指纹的解密密钥解密加密数据，以提取数据。 在一个实施例中，各种电路元件的传播延迟被用于产生指纹。 在另一个实施例中，使用振荡器的特定频率来生成指纹。 在另一个实施例中，使用可测量值的比例来生成指纹。 在另一个实施例中，晶体管阈值电压的差异用于产生指纹。 在另一个实施例中，使用线宽的变化来生成指纹。
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公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译： 在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表 ，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出 门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。 提供了一种用于在EDA工具上执行该方法的系统。 可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。
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7.发明授权Computer-readable storage media comprising data streams having mixed mode data correction capability 有权包括具有混合模式数据校正能力的数据流的计算机可读存储介质公开(公告)号：US07979826B1
公开(公告)日：2011-07-12
申请号：US11820938
申请日：2007-06-21
CPC分类号： G06F17/5054
摘要： Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.
摘要翻译： 在可编程逻辑器件（PLD）的配置比特流中提供纠错的方法。 虽然可以使用任何纠错方法，但是在一个实施例中，将汉明码应用于配置比特流中的指令，同时将产品代码应用于配置数据。 因此，汉明码所需的较高开销仅适用于比特流中的几个字。 在接收到包含汉明码的单词时纠正指令，因此即使发生传输错误，指令也能正确执行。 然而，配置数据可以存储在配置存储器中而不进行校正。 使用产品代码，当接收到奇偶校验字时，直到发送结束，才知道错误位的确切位置。 此时，在启用新加载的设计之前，PLD可以返回并纠正配置数据中的错误位。
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8.发明授权Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams 有权允许验证适合于接收多个配置比特流中的一个的集成电路的方法公开(公告)号：US07810059B1
公开(公告)日：2010-10-05
申请号：US11974387
申请日：2007-10-11
CPC分类号： G06F17/5054
摘要： Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.
摘要翻译： 公开了能够验证适合于接收电路设计的多个配置比特流中的一个的集成电路的方法。 该方法包括分析用于电路设计的多个实施方式; 基于电路设计的所有实现来确定最小时序约束; 基于满足所确定的电路设计的所有实现的最小时序约束的多个实现来生成代表性实现; 并输出代表性的实现。
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9.发明授权公开(公告)号：US07656189B1
公开(公告)日：2010-02-02
申请号：US11888198
申请日：2007-07-31
IPC分类号： G06F7/38 , H03K19/173 , H01L25/00
CPC分类号： H03K19/17768 , G06F21/76
摘要： Various approaches for detection of an unwanted function implemented in an integrated circuit (IC) are described. A controller is implemented on the IC, and at a first time while the IC is operating according to a circuit design, the controller reads a first data set from a subset of memory cells. The subset of memory cells stores state information of the circuit design. The controller determines whether the first data set is different from a second data set. In response to the first data set being different from the second data set, the controller outputs a threat signal that indicates the presence of unauthorized logic in the circuit design.
摘要翻译： 描述用于检测集成电路（IC）中实现的不期望功能的各种方法。 在IC上实现控制器，并且当IC根据电路设计操作时，第一时间，控制器从存储器单元的子集读取第一数据集。 存储器单元的子集存储电路设计的状态信息。 控制器确定第一数据集是否与第二数据集不同。 响应于第一数据集与第二数据集不同，控制器输出指示电路设计中存在未授权逻辑的威胁信号。
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10.发明授权公开(公告)号：US07590956B1
公开(公告)日：2009-09-15
申请号：US11818007
申请日：2007-06-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054 , G06F2217/10 , G06F2217/14 , G06F2217/78
摘要： Methods of detecting unwanted logic in an integrated circuit (IC) design. Any unwanted logic added to a design (e.g., to monitor or interfere with operation of the design) will draw power from one or more power supplies on the IC. Hence, by monitoring power drawn from various portions of a circuit design implemented in an IC, the unwanted logic can be detected and reported to the user. One way of monitoring power draw is by the use of oscillator circuits. If power goes down locally (e.g., due to the operation of unwanted logic), the frequency of an oscillator circuit in that vicinity will be reduced relative to the frequencies of other oscillator circuits in the design, and/or relative to an expected value. When a variation in the relative power consumption is detected, unwanted logic can be inferred and an error signal is output.
摘要翻译： 在集成电路（IC）设计中检测不需要的逻辑的方法。 添加到设计中的任何不想要的逻辑（例如，监视或干扰设计的操作）将从IC上的一个或多个电源获取电力。 因此，通过监视从IC中实现的电路设计的各个部分获得的功率，可以检测并且向用户报告不需要的逻辑。 监控功率的一种方法是使用振荡器电路。 如果电力局部下降（例如，由于不需要的逻辑的操作），则相邻的振荡器电路的频率将相对于设计中的其它振荡器电路的频率和/或相对于期望值而减小。 当检测到相对功率消耗的变化时，可以推断出不需要的逻辑并输出误差信号。
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