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    Slew rate control circuit
    1.
    发明授权
    Slew rate control circuit 有权
    压摆率控制电路

    公开(公告)号：US06744287B2

    公开(公告)日：2004-06-01

    申请号：US10225326

    申请日：2002-08-21

    申请人： Stephen R. Mooney ,  Joseph T. Kennedy ,  Chaiyuth Chansungsan ,  Prantik K. Nag

    发明人： Stephen R. Mooney ,  Joseph T. Kennedy ,  Chaiyuth Chansungsan ,  Prantik K. Nag

    IPC分类号： H03K1716

    CPC分类号： H04L25/0292 ,  H03K17/164 ,  H04L5/1423 ,  H04L25/0278 ,  H04L25/028

    摘要： A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

    摘要翻译： 双向通信系统包括能够控制发送的数据信号的转换速率的驱动器。 可以提供阻抗匹配以将驱动器电路的阻抗与通信线路的阻抗相匹配。 当数据从数据驱动器驱动时，阻抗保持不变。 数据接收器电路可以响应于同时发送的数据来调整参考电压。 控制接收器电路跳变点的转换速率，以在运行期间保持足够的噪声容限。 可以使用延迟线电路来控制接收器和驱动器电路。

    Point-to-point phase-tolerant communication
    3.
    发明授权
    Point-to-point phase-tolerant communication 失效
    点对点相容通信

    公开(公告)号：US5623644A

    公开(公告)日：1997-04-22

    申请号：US296019

    申请日：1994-08-25

    申请人： Keith-Michael W. Self ,  Shekhar Y. Borkar ,  Jerry G. Jex ,  Edward A. Burton ,  Stephen R. Mooney ,  Prantik K. Nag

    发明人： Keith-Michael W. Self ,  Shekhar Y. Borkar ,  Jerry G. Jex ,  Edward A. Burton ,  Stephen R. Mooney ,  Prantik K. Nag

    IPC分类号： G06F15/173 ,  G06F13/00 ,  G06F15/16

    CPC分类号： G06F15/17381

    摘要： A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.

    摘要翻译： 一种单向点对点通信装置，用于在两个计算资源之间传送消息，而不管消息的相位，两个计算资源之间的通信路径的长度以及两个计算资源的内部速度。 通信装置具有耦合发射机和接收机的高速通信总线，用于将消息从发射机发射到接收机。 高速通信时钟耦合到总线和接收器，用于定时在发射机和接收机之间的高速通信总线上发送的消息。 在用于存储在发射机和接收机之间传输的消息的接收机之后，大数据缓冲器耦合到高速通信总线。 缓冲器访问电路耦合到缓冲器，用于参考写入位置以存储通过通信总线从发送器接收的消息，并且用于参考由接收器读出缓冲器中的消息的读取位置。 最后，延迟锁定环路电路耦合到通信总线，缓冲器访问电路和缓冲器，用于为在通信总线上从发送器发送的消息提供适当的建立和保持时间要求，并将消息存储在缓冲器中 。

    Output buffer with adjustment of signal transitions
    4.
    发明授权
    Output buffer with adjustment of signal transitions 失效
    具有调整信号转换的输出缓冲器

    公开(公告)号：US07005903B2

    公开(公告)日：2006-02-28

    申请号：US10726297

    申请日：2003-12-02

    申请人： Hong H. Chan ,  Jeffrey E. Smith ,  Yongping Fan ,  Prantik K. Nag

    发明人： Hong H. Chan ,  Jeffrey E. Smith ,  Yongping Fan ,  Prantik K. Nag

    IPC分类号： H03K5/12

    CPC分类号： H03K19/00384

    摘要： An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped waveform to trigger the LH and HL signal transitions of the output signal, with the first stage generating an initial waveform and the second stage modifying the initial waveform to generate the reshaped waveform based at least in part on a feedback reflective of a difference in the clock-to-output delays of the LH and HL signal transitions.

    摘要翻译： 输出缓冲器产生具有多个低到高（LH）和高到低（HL）信号转换的输出信号，其中每个信号转换具有时钟到输出延迟。 具有第一和第二阶段的预驱动器产生重构波形以触发输出信号的LH和HL信号转换，其中第一级产生初始波形，第二级修改初始波形以产生基于重新形成的波形 至少部分地基于反映LH和HL信号转换的时钟到输出延迟的差异的反馈。