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32 条记录 (耗时 0.033 秒)

    Slew rate control circuit
    2.
    发明授权
    Slew rate control circuit 有权
    压摆率控制电路

    公开(公告)号：US06744287B2

    公开(公告)日：2004-06-01

    申请号：US10225326

    申请日：2002-08-21

    申请人： Stephen R. Mooney ,  Joseph T. Kennedy ,  Chaiyuth Chansungsan ,  Prantik K. Nag

    发明人： Stephen R. Mooney ,  Joseph T. Kennedy ,  Chaiyuth Chansungsan ,  Prantik K. Nag

    IPC分类号： H03K1716

    CPC分类号： H04L25/0292 ,  H03K17/164 ,  H04L5/1423 ,  H04L25/0278 ,  H04L25/028

    摘要： A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

    摘要翻译： 双向通信系统包括能够控制发送的数据信号的转换速率的驱动器。 可以提供阻抗匹配以将驱动器电路的阻抗与通信线路的阻抗相匹配。 当数据从数据驱动器驱动时，阻抗保持不变。 数据接收器电路可以响应于同时发送的数据来调整参考电压。 控制接收器电路跳变点的转换速率，以在运行期间保持足够的噪声容限。 可以使用延迟线电路来控制接收器和驱动器电路。

    Simultaneous transmission and reception of signals in different frequency bands over a bus line
    3.
    发明授权
    Simultaneous transmission and reception of signals in different frequency bands over a bus line 有权
    在总线上同时发送和接收不同频段的信号

    公开(公告)号：US07177288B2

    公开(公告)日：2007-02-13

    申请号：US09998008

    申请日：2001-11-28

    申请人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    发明人： Stephen R. Mooney ,  Aaron K. Martin ,  Matthew B. Haycock ,  Bryan K. Casper ,  Shekhar Y. Borkar ,  Joseph T. Kennedy ,  James E. Jaussi

    IPC分类号： H04L5/14

    CPC分类号： H04L5/1423

    摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

    摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。

    Fixed phase clock and strobe signals in daisy chained chips
    4.
    发明授权
    Fixed phase clock and strobe signals in daisy chained chips 失效
    在菊花链芯片中固定相位时钟和选通信号

    公开(公告)号：US07031221B2

    公开(公告)日：2006-04-18

    申请号：US10749677

    申请日：2003-12-30

    申请人： Stephen R. Mooney ,  Joseph T. Kennedy

    发明人： Stephen R. Mooney ,  Joseph T. Kennedy

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1066 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1093

    摘要： In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，芯片包括分别提供第一和第二接收数据信号的第一和第二端口以及第一和第二接收选通信号。 内部时钟信号与第一接收选通信号具有固定的相位关系，第二接收选通信号与内部时钟信号具有任意的相位关系。 第一和第二写入块分别与第一和第二接收选通信号同步地锁存第一和第二接收数据信号。 描述和要求保护其他实施例。

    Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference
    6.
    发明授权
    Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference 有权
    使用从动到闭环定时参考的匹配的受控延迟元件来最小化抖动的方法

    公开(公告)号：US06774686B2

    公开(公告)日：2004-08-10

    申请号：US09968460

    申请日：2001-09-28

    申请人： Joseph T. Kennedy ,  Bryan K. Casper ,  Stephen R. Mooney ,  Aaron K. Martin

    发明人： Joseph T. Kennedy ,  Bryan K. Casper ,  Stephen R. Mooney ,  Aaron K. Martin

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  H03L7/0812

    摘要： A method for minimizing jitter using substantially matched, controlled, delay elements is disclosed. The method includes generating an internal loop-timing reference, and controlling elements outside of the loop with the internal loop-timing reference generated. In one embodiment the outside elements are substantially identical to those internal to the closed-loop. Controlled delay elements for preconditioning and distributing closed-loop inputs and outputs, using the same control reference used by internal loop elements are disclosed.

    摘要翻译： 公开了一种使用基本匹配的受控延迟元件来最小化抖动的方法。 该方法包括生成内部循环定时参考，以及生成内部循环定时参考，控制环外的元素。 在一个实施例中，外部元件与闭环内部元件基本相同。 公开了用于预调节和分配闭环输入和输出的受控延迟元件，使用与内部环路元件相同的控制参考。

    Using a timing strobe for synchronization and validation in a digital logic device
    7.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
    8.
    发明授权
    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
    具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化

    公开(公告)号：US06373289B1

    公开(公告)日：2002-04-16

    申请号：US09752895

    申请日：2000-12-26

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： H03K1900

    CPC分类号： H03L7/0812 ,  H03K5/135 ,  H04L25/242

    摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

    摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。

    Impedance control circuit
    9.
    发明授权
    Impedance control circuit 失效
    阻抗控制电路

    公开(公告)号：US6087847A

    公开(公告)日：2000-07-11

    申请号：US902345

    申请日：1997-07-29

    申请人： Stephen R. Mooney ,  Matthew B. Haycock ,  Joseph T. Kennedy

    发明人： Stephen R. Mooney ,  Matthew B. Haycock ,  Joseph T. Kennedy

    IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/003

    CPC分类号： H03K19/017545 ,  H03K19/0005

    摘要： Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

    摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括：数字反馈控制电路，用于至少部分地基于调整了非数据信号输出缓冲器的阻抗来调整接口电路输出缓冲器的阻抗 耦合到外部阻抗。 简而言之，根据本发明的另一个实施例，一种数字调节接口电路输出缓冲器的阻抗的方法包括：数字调节耦合到外部阻抗的非数据信号输出缓冲器的阻抗，并数字调节阻抗 所述接口电路输出缓冲器至少部分地基于非数据信号输出缓冲器的数字调节阻抗。