公开(公告)号：US09379717B2

公开(公告)日：2016-06-28

申请号：US14129505

申请日：2013-11-08

Applicant: Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

Inventor： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

IPC: H03L7/00 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089

CPC classification number: H03L7/0802 ,  H03L7/085 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/093

Abstract: Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

Abstract translation: 描述了一种降低电荷泵功率的装置。 所述装置包括：第一延迟单元，用于接收参考时钟，所述第一延迟单元向第一顺序单元提供延迟的参考时钟; 第二延迟单元，用于接收反馈时钟，所述第二延迟单元向第二顺序单元提供延迟的反馈时钟; 用于接收参考和反馈时钟的第一逻辑单元，所述逻辑单元对所接收的参考和反馈时钟执行逻辑或运算，并且产生用于第三顺序单元的触发信号; 以及第二逻辑单元，用于接收第一和第二顺序单元的输出，并且产生耦合到第三顺序单元的输出。

公开(公告)号：US08274339B2

公开(公告)日：2012-09-25

申请号：US12770230

申请日：2010-04-29

Applicant: Yongping Fan ,  Jing Li ,  Ian A. Young

Inventor： Yongping Fan ,  Jing Li ,  Ian A. Young

IPC: H03L1/02 ,  H03L7/085

CPC classification number: H03L1/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1265 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract translation: 公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。 一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。 在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。 此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。 在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

公开(公告)号：US20080122507A1

公开(公告)日：2008-05-29

申请号：US11592594

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0891

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.

Abstract translation: 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。

公开(公告)号：US20070063749A1

公开(公告)日：2007-03-22

申请号：US11232840

申请日：2005-09-21

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K2005/00039

Abstract: Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being coupled to a vp-bias and gates of the NMOS portion being coupled to a vn-bias, the delay cell further being coupled to a reference clock to drive a pulse output of the delay cell, a first bias generation circuit to generate the vn-bias based on a phase comparison of the pulse output to the reference clock, and a second bias generation circuit to generate the vp-bias based on a reference voltage and the vn-bias.

Abstract translation: 描述了基于可用于半导体器件之间的定时数据接口的这样的单元的匹配的当前延迟单元和延迟锁定环。 在一个实施例中，延迟单元包括具有PMOS部分和NMOS部分的延迟单元，PMOS部分的栅极耦合到vp偏置，并且NMOS部分的栅极耦合到vn偏置，延迟单元进一步 耦合到参考时钟以驱动所述延迟单元的脉冲输出;第一偏置产生电路，用于基于所述脉冲输出与所述参考时钟的相位比较产生所述vn偏置;以及第二偏置产生电路， 基于参考电压和vn偏置的vp偏置。

公开(公告)号：US5782996A

公开(公告)日：1998-07-21

申请号：US520443

申请日：1995-08-29

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H01L33/28 ,  H01L33/40 ,  H01S5/00 ,  H01S5/327 ,  C30B29/49

CPC classification number: H01L33/40 ,  H01L33/28 ,  H01S5/327

Abstract: A graded layer composition of Zn(Se,Te) in which the Te fraction varies across the layer in a super-parabolic grading profile. Such a graded layer has lower contact resistance than graded layers in which the Te fraction varies in a linear or parabolic grading profile. Such low contact resistance makes such graded layers useful in forming ohmic contacts for II-VI semiconductor lasers and light emitting diodes.

Abstract translation: Zn（Se，Te）的梯度层组合物，其中Te部分在超抛物线分级轮廓中跨越该层而变化。 这样的梯度层具有比梯度层更低的接触电阻，其中Te部分以线性或抛物线分级轮廓变化。 这种低接触电阻使得这种渐变层可用于形成用于II-VI半导体激光器和发光二极管的欧姆接触。

公开(公告)号：US09231519B2

公开(公告)日：2016-01-05

申请号：US13976942

申请日：2012-03-13

Applicant: Fangxing Wei ,  Yongping Fan

Inventor： Fangxing Wei ,  Yongping Fan

IPC: H03L1/00 ,  H03B5/04 ,  H03B5/12

CPC classification number: H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265

Abstract: A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.

Abstract translation: 温度补偿装置可以包括被配置为产生取决于温度的感测电压的感测电路和被配置为接收感测电压并产生温度补偿控制信号以控制振荡器的补偿电容器阵列的温度补偿电路。 温度补偿电路可以被配置为校准控制信号以具有处于第一温度的第一值。 温度补偿电路还可以被配置为校准控制信号的微调电平（例如，斜率）。

公开(公告)号：US20140266472A1

公开(公告)日：2014-09-18

申请号：US13837070

申请日：2013-03-15

Applicant: Jeffrey W. Waldrip ,  Yongping Fan ,  Jing Li

Inventor： Jeffrey W. Waldrip ,  Yongping Fan ,  Jing Li

IPC: H03L1/02

CPC classification number: H03L1/022 ,  H03B5/04 ,  H03B5/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/103 ,  H03L2207/06 ,  H04L7/033

Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Abstract translation: 在一些实施例中，提供了AFC电路和用于校准振荡器的第二设置的方法，而第一设置由温度补偿控制来控制。

公开(公告)号：US20140218082A1

公开(公告)日：2014-08-07

申请号：US13997645

申请日：2011-12-30

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/093

CPC classification number: H03L7/093 ,  H03H19/004 ,  H03L7/0893

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract translation: 描述环路滤波器。 环路滤波器具有第一和第二输入和输出。 环路滤波电容器耦合到环路滤波器输出。 采样开关耦合到第二环路滤波器输入。 分压器耦合到复位开关。 开关电容器耦合到采样开关，复位开关，环路滤波电容器和环路滤波器输出。

公开(公告)号：US07501869B2

公开(公告)日：2009-03-10

申请号：US11592594

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0891

Abstract: A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.

Abstract translation: 一种用于源同步数字数据通信的时钟接收器架构，接收器包括转发的时钟放大器，以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号，其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻（相对于相位）时钟信号之间插值，以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中，片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中，锁相环和相位内插器中的上拉电流和下拉电流在过程，电源电压和温度变化之间匹配，使得时钟信号的相对相位在过程，电源电压和 温度变化。 描述和要求保护其他实施例。

公开(公告)号：US20070216454A1

公开(公告)日：2007-09-20

申请号：US11374808

申请日：2006-03-14

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0891 ,  H03L7/10

Abstract: A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The charge pump generates an operational bias voltage during operation of the first circuit to control a delay of the delay cells. A fast lock circuit is coupled to an output of the charge pump to precharge the output of the charge pump with a startup bias voltage prior to enabling the charge pump.

Abstract translation: 用于延迟锁定环和锁相环的快速锁定机制。 第一电路被耦合以接收输入时钟信号并响应于输入时钟信号产生输出时钟信号。 第一电路包括电荷泵和延迟单元。 电荷泵在第一电路的操作期间产生操作偏置电压以控制延迟单元的延迟。 快速锁定电路耦合到电荷泵的输出端，以在启用电荷泵之前以启动偏置电压对电荷泵的输出进行预充电。