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26 条记录 (耗时 0.024 秒)

    Flexible, high-performance static RAM architecture for field-programmable gate arrays
    5.
    发明授权
    Flexible, high-performance static RAM architecture for field-programmable gate arrays 失效
    用于现场可编程门阵列的灵活高性能静态RAM架构

    公开(公告)号：US5744980A

    公开(公告)日：1998-04-28

    申请号：US603597

    申请日：1996-02-16

    申请人： John E. McGowan ,  William C. Plants ,  Joel D. Landry ,  Sinan Kaptanoglu ,  Warren K. Miller

    发明人： John E. McGowan ,  William C. Plants ,  Joel D. Landry ,  Sinan Kaptanoglu ,  Warren K. Miller

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17704

    摘要： A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.

    摘要翻译： 现场可编程门阵列架构包括多个水平和垂直路由通道，每个路由通道包括多个互连导体。 一些互连导体由用户可编程互连元件分段，并且一些水平和垂直互连导体可由位于它们之间的选定交叉处的用户可编程互连元件连接。 每个具有至少一个输入和一个输出的逻辑功能模块的行和列阵列叠加在路由信道上。 逻辑功能模块的输入和输出可连接到水平和垂直路由通道中的一个或两者中的互连导体中的一个。 至少一列随机存取存储器块被布置在阵列中。 每个随机存取存储器块跨越阵列的多于一行的距离，使得多于一个的水平路由信道通过其中并且可连接到其任一侧的相邻逻辑功能模块。 每个随机存取存储块具有地址输入，控制输入，数据输入和数据输出。 用户可编程互连元件连接在随机存取存储器块的地址输入，控制输入，数据输入和数据输出以及通过其中的水平路由通道中的选定的互连导体。 提供了编程电路，用于编程用户可编程互连导体中的所选择的一个以将逻辑功能模块的输入和输出彼此连接，并将随机存取存储器块的地址输入，控制输入，数据输入和数据输出 。

    Fast wide decode in an FPGA using probe circuit
    8.
    发明授权
    Fast wide decode in an FPGA using probe circuit 失效
    使用探针电路在FPGA中快速解码

    公开(公告)号：US5952852A

    公开(公告)日：1999-09-14

    申请号：US887380

    申请日：1997-07-02

    申请人： John E. McGowan ,  William C. Plants ,  Warren K. Miller

    发明人： John E. McGowan ,  William C. Plants ,  Warren K. Miller

    IPC分类号： G01R31/3185 ,  H03K19/177 ,  H03K19/08

    CPC分类号： G01R31/318519

    摘要： In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at least one logic module associated with the test probe circuit, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.In a second aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a plurality of test probe circuits, each associated with a column in the array, selecting at least one logic module associated with each of the test probe circuits, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.

    摘要翻译： 在本发明的第一方面，通过选择与阵列中的列相关联的测试探针电路，在现场可编程门阵列中实现快速，宽的解码，选择与测试探针电路相关联的至少一个逻辑模块，驱动 通过所述至少一个逻辑模块的输出在所述至少一个逻辑模块中测试探针电路，并感测所述测试探针电路中的逻辑电平，以确定是否发生在所述至少一个逻辑模块的输入处的解码中的匹配 。 在本发明的第二方面中，通过选择多个测试探针电路来实现现场可编程门阵列中的快速，宽的解码，每个测试探针电路与阵列中的列相关联，选择至少一个逻辑模块 测试探针电路，通过所述至少一个逻辑模块的输出驱动所述至少一个逻辑模块中的所述测试探针电路，并且感测所述测试探针电路中的逻辑电平，以确定在所述至少一个逻辑模块的输入处的解码中是否匹配 发生了至少一个逻辑模块。

    Solvent-resistant microporous polymide membranes
    9.
    发明授权
    Solvent-resistant microporous polymide membranes 失效
    耐溶剂微孔聚酰亚胺膜

    公开(公告)号：US5725769A

    公开(公告)日：1998-03-10

    申请号：US503809

    申请日：1995-07-18

    申请人： Warren K. Miller ,  Scott B. McCray ,  Dwayne T. Friesen

    发明人： Warren K. Miller ,  Scott B. McCray ,  Dwayne T. Friesen

    IPC分类号： B01D71/64 ,  C08G73/10 ,  B01D53/22

    CPC分类号： C08G73/1042 ,  B01D71/64

    摘要： An asymmetric microporous membrane with exceptional solvent resistance and highly desirable permeability is disclosed. The membrane is made by a solution-casting or solution-spinning process from a copolyamic acid comprising the condensation reaction product in a solvent of at least three reactants selected from certain diamines and dianhydrides and post-treated to imidize and in some cases cross-link the copolyamic acid. The membrane is useful as an uncoated membrane for ultrafiltration, microfiltration, and membrane contactor applications, or may be used as a support for a permselective coating to form a composite membrane useful in gas separations, reverse osmosis, nanofiltration, pervaporation, or vapor permeation.

    摘要翻译： 公开了具有优异的耐溶剂性和高度期望的渗透性的不对称微孔膜。 该膜通过溶液浇铸或溶液纺丝方法从包含缩合反应产物的共聚酰胺酸在至少三种选自某些二胺和二酸酐的反应物的溶剂中制备，并经过后处理以酰亚胺化，并且在某些情况下交联 共聚酰胺酸。 该膜可用作用于超滤，微滤和膜接触器应用的未涂覆膜，或者可用作用于选择性渗透涂层以形成用于气体分离，反渗透，纳滤，渗透蒸发或蒸汽渗透的复合膜的载体。