公开(公告)号：US07575984B2

公开(公告)日：2009-08-18

申请号：US11444936

申请日：2006-05-31

申请人： Steven J Radigan ,  Usha Raghuram ,  Samuel V Dunton ,  Michael W Konevecki

发明人： Steven J Radigan ,  Usha Raghuram ,  Samuel V Dunton ,  Michael W Konevecki

IPC分类号： H01L21/326 ,  H01L21/82 ,  H01L21/44

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.

摘要翻译： 提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。 硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。 该方法有利地用于形成单片三维存储器阵列。

公开(公告)号：US07422985B2

公开(公告)日：2008-09-09

申请号：US11090526

申请日：2005-03-25

申请人： Samuel V Dunton ,  Christopher J Petti ,  Usha Raghuram

发明人： Samuel V Dunton ,  Christopher J Petti ,  Usha Raghuram

IPC分类号： H01L21/302

CPC分类号： H01L27/1021 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/90

摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

摘要翻译： 基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。 在优选实施例中，导电或半导体特征是形成垂直取向的二极管的柱。 不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。 选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。 在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或 半导体功能。

公开(公告)号：US07291562B2

公开(公告)日：2007-11-06

申请号：US11298015

申请日：2005-12-09

申请人： Yung-Tin Chen ,  Samuel V Dunton

发明人： Yung-Tin Chen ,  Samuel V Dunton

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/544 ,  H01L23/585 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/105 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.

摘要翻译： 在本发明中，在第一沉积层中形成虚拟结构，以便在形成于第一沉积层之上和之后的沉积层中形成一般凸起区域的形貌。 这种形态在后面的步骤中可能是有利的。 在一个实施例中，转移的形貌允许由不透明层遮蔽的对准或覆盖标记由该增强的形貌定位。 在另一个实施例中，凸起体积的介电材料防止阵列区域外部的特征在CMP步骤期间被过度抛光。 这种方法也可能在其他情况下也是有用的。 调整虚拟结构的大小，形状和位置以形成所需的过剩体积。