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    Dual damascene with amorphous carbon for 3D deep via/trench application
    1.
    发明授权
    Dual damascene with amorphous carbon for 3D deep via/trench application 有权
    双重镶嵌无定形碳，用于3D深通孔/沟槽应用

    公开(公告)号：US08298931B2

    公开(公告)日：2012-10-30

    申请号：US11864759

    申请日：2007-09-28

    申请人： Usha Raghuram ,  Michael W. Konevecki

    发明人： Usha Raghuram ,  Michael W. Konevecki

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L27/101 ,  H01L27/1021

    摘要： A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.

    摘要翻译： 一种用于制造使用无定形碳硬掩模蚀刻通孔和​​沟槽的3-D单片存储器件的方法。 该通孔作为多级垂直互连在设备的多个级别中延伸。 沟槽横向延伸，例如为存储器单元提供字线或位线，或提供其它布线路径。 可以使用双镶嵌工艺，其中通孔首先形成并且沟槽形成第二，或者沟槽首先形成，并且通孔形成第二。 该技术特别适用于深通孔应用，例如大于1μm的通孔深度。 可以使用任选具有底部抗反射涂层的电介质抗反射涂层来蚀刻无定形碳层以提供无定形碳硬掩模。

    Nonselective unpatterned etchback to expose buried patterned features
    4.
    发明授权
    Nonselective unpatterned etchback to expose buried patterned features 失效
    曝光掩埋图案特征的无选择性无图案蚀刻

    公开(公告)号：US07307013B2

    公开(公告)日：2007-12-11

    申请号：US10883417

    申请日：2004-06-30

    申请人： Usha Raghuram ,  Michael W. Konevecki ,  Samuel V. Dunton

    发明人： Usha Raghuram ,  Michael W. Konevecki ,  Samuel V. Dunton

    IPC分类号： H01L21/461 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L21/7684 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/76819 ,  H01L27/101 ,  H01L27/1021

    摘要： A method for etching to form a planarized surface is disclosed. Spaced-apart features are formed of a first material, the first material either conductive or insulating. A second material is deposited over and between the first material. The second material is either insulating or conductive, opposite the conductivity of the first material. The second material is preferably self-planarizing during deposition. An unpatterned etch is performed to etch the second material and expose the top of the buried features of the first material. The etch is preferably a two-stage etch: The first stage is selective to the second material. When the second material is exposed, the etch chemistry is changed such that the etch is nonselective, etching the first material and the second material at substantially the same rate until the buried features are exposed across the wafer, producing a substantially planar surface.

    摘要翻译： 公开了一种用于蚀刻以形成平坦化表面的方法。 隔开的特征由第一材料形成，第一材料是导电的或绝缘的。 第二材料沉积在第一材料之上和之间。 第二种材料是绝缘的或导电的，与第一种材料的电导率相反。 第二种材料优选在沉积期间是自平面化的。 执行未图案化的蚀刻以蚀刻第二材料并暴露第一材料的掩埋特征的顶部。 蚀刻优选是两阶段蚀刻：第一阶段对第二材料是选择性的。 当暴露第二材料时，蚀刻化学物质被改变，使得蚀刻是非选择性的，以基本上相同的速率蚀刻第一材料和第二材料，直到掩埋特征暴露在晶片之外，产生基本平坦的表面。

    Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon
    9.
    发明授权
    Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon 有权
    使用无定形碳上的氮氧化硅硬掩模制造3-D集成电路的方法

    公开(公告)号：US07718546B2

    公开(公告)日：2010-05-18

    申请号：US11769027

    申请日：2007-06-27

    申请人： Steven J. Radigan ,  Michael W. Konevecki

    发明人： Steven J. Radigan ,  Michael W. Konevecki

    IPC分类号： H01L21/469

    CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/0688 ,  H01L29/8615 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

    摘要翻译： 一种用于制造3-D单片存储器件的方法。 无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。 使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。 使用无定形碳层蚀刻硅，氧化物和/或钨层。 在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。 通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。 与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

    CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH
    10.
    发明申请
    CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
    导电硬掩模，以保护在TRENCH ETCH期间的图案特征

    公开(公告)号：US20090273022A1

    公开(公告)日：2009-11-05

    申请号：US12502796

    申请日：2009-07-14

    申请人： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

    发明人： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

    IPC分类号： H01L27/105 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06

    CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.

    摘要翻译： 单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱， 柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽 所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率 开关金属氧化物或氮化物。 该方法还包括在第一存储器级上方单片地形成第二存储器级。 还描述了其他方面。